K5A3x80YT(B)C
Multi-Chip Package MEMORY
Preliminary
MCP MEMORY
32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 8M(1Mx8/512Kx16) Full CMOS SRAM
FEATURES
•
Power Supply voltage : 2.7V to 3.3V
•
Organization
- Flash : 4,194,304 x 8 / 2,097,152 x 16 bit
- SRAM : 1,048,576 x 8 / 524,288 x 16 bit
•
Access Time (@2.7V)
- Flash : 70 ns, SRAM : 55 ns
•
Power Consumption (typical value)
- Flash Read Current : 14 mA (@5MHz)
Program/Erase Current : 15 mA
Standby mode/Autosleep mode : 5
µA
Read while Program or Read while Erase : 25 mA
- SRAM Operating Current : 22 mA
Standby Current : 0.5
µA
•
Secode(Security Code) Block : Extra 64KB Block (Flash)
•
Block Group Protection / Unprotection (Flash)
•
Flash Bank Size : 8Mb / 24Mb , 16Mb / 16Mb
•
Flash Endurance : 100,000 Program/Erase Cycles Minimum
•
SRAM Data Retention : 1.5 V (min.)
•
Industrial Temperature : -40°C ~ 85°C
•
Package : 69-ball TBGA Type - 8 x 11mm, 0.8 mm pitch
1.2mm(max.) Thickness
GENERAL DESCRIPTION
The K5A3x80YT(B)C featuring single 3.0V power supply is a
Multi Chip Package Memory which combines 32Mbit Dual Bank
Flash and 8Mbit fCMOS SRAM.
The 32Mbit Flash memory is organized as 4M x8 or 2M x16 bit
and 8Mbit SRAM is organized as 1M x8 or 512K x16 bit. The
memory architecture of flash memory is designed to divide its
memory arrays into 71 blocks and this provides highly flexible
erase and program capability. This device is capable of reading
data from one bank while programming or erasing in the other
bank with dual bank organization.
The Flash memory performs a program operation in units of 8 bits
(Byte) or 16 bits (Word) and erases in units of a block. Single or
multiple blocks can be erased. The block erase operation is com-
pleted for typically 0.7sec.
The 8Mbit SRAM supports low data retention voltage for battery
backup operation with low data retention current.
The K5A3x80YT(B)C is suitable for the memory of mobile com-
munication system to reduce mount area. This device is available
in 69-ball TBGA Type package.
BALL CONFIGURATION
BALL DESCRIPTION
Ball Name
A
0
to A
18
Description
Address Input Balls (Common)
Address Input Balls (Flash Memory)
Data Input/Output Balls (Common)
Hardware Reset (Flash Memory)
Write Protection / Acceleration Program
(Flash Memory)
Power Supply (SRAM)
Power Supply (Flash Memory)
Ground (Common)
Upper Byte Enable (SRAM)
Lower Byte Enable (SRAM)
BYTE
S
Control (SRAM)
BYTE
F
Control (Flash Memory)
Address Inputs (SRAM)
Chip Enable (Flash Memory)
Chip Enable (SRAM Low Active)
Chip Enable (SRAM High Active)
Write Enable (Common)
Output Enable (Common)
Ready/Busy (Flash memory)
No Connection
1
A
B
C
D
E
F
G
H
J
K
N.C
N.C
N.C
2
3
4
5
N.C
WP/
ACC
6
N.C
7
8
9
10
N.C
A-1, A
19
to A
20
DQ
0
to DQ
15
RESET
N.C
A3
A2
A1
A7
LB
WE
CS2
S
A20
A8
A11
WP/ACC
A15
N.C
A6
A5
UB
A18
A17
RESET
A19
A12
Vcc
S
Vcc
F
Vss
N.C
RY/BY
A9
A13
A4
A10
A14
N.C
UB
LB
BYTE
S
BYTE
F
SA
CE
F
N.C
A0
CE
F
CS1
S
V
SS
DQ1
DQ6
SA
A16
N.C
OE
DQ9
DQ3
DQ4
Vcc
S
DQ13
DQ15
BYTE
F
/A-1
DQ12 DQ7
Vss
DQ0
DQ10 Vcc
F
DQ8
DQ2
DQ11
BYTES
DQ5 DQ14
CS1
S
N.C
N.C
N.C
CS2
S
WE
OE
69 Ball TBGA , 0.8mm Pitch
RY/BY
N.C
Top View (Ball Down)
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
-2-
Revision 0.0
November 2002
ARM Technology
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EEWORLD
