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Data Sheet
N O R o ur Te o r w w
IL
act
cont -INTERS
8
1-88
HI5905
March 2003
FN4259.4
14-Bit, 5MSPS A/D Converter
The HI5905 is a monolithic, 14-bit, 5MSPS Analog-to-
Digital Converter fabricated in an advanced BiCMOS
process. It is designed for high speed, high resolution
applications where wide bandwidth, low power
consumption and excellent SINAD performance are
essential. With a 100MHz full power input bandwidth and
high frequency accuracy, the converter is ideal for many
types of communication systems employing digital IF
architectures.
The HI5905 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold amplifier (S/H). The HI5905 has excellent
dynamic performance while consuming 350mW power at
5MSPS.
Data output latches are provided which present valid data to
the output bus with a low data latency of 4 clock cycles.
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MSPS
• Low Power at 5MSPS . . . . . . . . . . . . . . . . . . . . . .350mW
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• SINAD at 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . >70dB
• Low Data Latency
• Internal Voltage Reference
• TTL Compatible Clock Input
• CMOS Compatible Digital Data Outputs
Applications
• Digital Communication Systems
• Undersampling Digital IF
Part Number Information
PART
NUMBER
HI5905IN
HI5905EVAL2
TEMP. RANGE
(
o
C)
-40 to 85
25
PACKAGE
44 Ld MQFP
PKG.
NO.
Q44.10x10
• Asymmetric Digital Subscriber Line (ADSL)
• Document Scanners
• Reference Literature
- AN9214, Using Intersil High Speed A/D Converters
- AN9785, Using the Intersil HI5905 EVAL2 Evaluation
Board
Low Frequency Eval Platform
Pinout
HI5905 (MQFP)
TOP VIEW
DV
CC1
D
GND1
DV
CC1
CLK
NC
NC
NC
NC
NC
D
GND1
NC
AV
CC
A
GND
NC
NC
V
IN+
V
IN-
V
DC
1
44 43 42 41 40 39 38 37 36 35 34
33
2
32
3
4
5
6
7
8
9
31
30
29
28
27
26
25
24
NC
D0
D1
D2
D3
D4
D5
D6
D7
NC
DV
CC2
D
GND2
D8
D9
NC
10
11
23
12 13 14 15 16 17 18 19 20 21 22
A
GND
V
ROUT
AV
CC
V
RIN
NC
NC
D13
D12
D11
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
D10
NC
HI5905
Functional Block Diagram
V
DC
V
IN
-
V
IN
+
S/H
STAGE 1
DV
CC2
BIAS
CLOCK
REF
CLK
V
ROUT
V
RIN
4-BIT
FLASH
+
4-BIT
DAC
D13 (MSB)
D12
D11
DIGITAL DELAY
AND
DIGITAL ERROR CORRECTION
D10
D9
D8
D7
D6
D5
D4
D3
D2
∑
-
X8
STAGE 4
4-BIT
FLASH
+
4-BIT
DAC
∑
X8
-
D1
D0 (LSB)
STAGE 5
4-BIT
FLASH
D
GND2
AV
CC
A
GND
DV
CC1
D
GND1
Typical Application Schematic
(LSB) D0 (38)
D1 (37)
D2 (36)
V
RIN
(14)
D3 (33)
A
GND
(6)
D4 (32)
A
GND
(15)
D5 (31)
D
GND1
(3)
D6 (30)
D
GND1
(42)
D7 (29)
D
GND2
(26)
D8 (25)
V
IN
+ (9)
D9 (24)
D10 (21)
V
DC
(11)
D11 (20)
V
IN
- (10)
D12 (19)
(MSB) D13 (18)
V
ROUT
(13)
CLK (40)
DV
CC1
(41)
AV
CC
(5) DV
CC1
(43)
+5V
+
10µF
AV
CC
(16)DV
CC2
(27)
0.1µF
HI5905
0.1µF
+
10µF
+5V
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D
GND
A
GND
BNC
V
IN
+
V
IN
-
CLOCK
10µF AND 0.1µF CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE
2
HI5905
Absolute Maximum Ratings
Supply Voltage, AV
CC
or DV
CC
to A
GND
or D
GND
. . . . . . . . . +6.0V
D
GND
to A
GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D
GND
to DV
CC
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A
GND
to AV
CC
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
Operating Conditions
Temperature Range (HI5905IN) . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
CC
= DV
CC1
= DV
CC2
= +5.0V, f
S
= 5MSPS at 50% Duty Cycle, V
RIN
= V
ROUT
, C
L
= 15pF,
T
A
= 25
o
C, Differential Analog Input, Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
ACCURACY
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
Offset Error, V
OS
Full Scale Error, FSE
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
Maximum Conversion Rate
Effective Number of Bits, ENOB
Signal to Noise and Distortion Ratio, SINAD
RMS Signal
-
=
-------------------------------------------------------------
RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
-
=
------------------------------
RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
Transient Response
Over-Voltage Recovery
ANALOG INPUT
Maximum Peak-to-Peak Differential Analog Input Range (V
IN
+
- V
IN
-)
Maximum Peak-to-Peak Single-Ended Analog Input Range
Analog Input Resistance, R
IN
Analog Input Capacitance, C
IN
Analog Input Bias Current, I
B
+ or I
B
-
Differential Analog Input Bias Current I
B DIFF
= (I
B
+ - I
B
-)
14
Sinewave Histogram
Sinewave Histogram
f
IN
= DC
f
IN
= DC
-
-1
-
-
-
±
2.5
±0.5
-
-
-
-
+1.5
120
164
Bits
LSB
LSB
LSB
LSB
No Missing Codes (Note 2)
No Missing Codes
f
IN
= 1MHz
f
IN
= 1MHz
-
5
11.2
69
-
-
11.7
72.2
0.5
-
-
-
MSPS
MSPS
Bits
dB
f
IN
= 1MHz
71
74.6
-
dB
f
IN
= 1MHz
f
IN
= 1MHz
f
IN
= 1MHz
f
IN
= 1MHz
f
1
= 1MHz, f
2
= 1.02MHz
-73
-
-
80
-
-
75.7
-95
-77
-
74
1
2
-
dBc
dBc
-
-
-
-
-
dBc
dBc
dBc
Cycle
Cycle
0.2V Overdrive
-
-
-
(Notes 1, 2)
(Note 2)
(Note 3)
1
-
-50
-
±2.0
4.0
-
10
-
±0.5
-
-
-
16
+50
-
V
V
MΩ
pF
µA
µA
3
HI5905
Electrical Specifications
AV
CC
= DV
CC1
= DV
CC2
= +5.0V, f
S
= 5MSPS at 50% Duty Cycle, V
RIN
= V
ROUT
, C
L
= 15pF,
T
A
= 25
o
C, Differential Analog Input, Unless Otherwise Specified
(Continued)
TEST CONDITIONS
MIN
-
Differential Mode (Note 2)
1
TYP
100
2.3
MAX
-
4
UNITS
MHz
V
PARAMETER
Full Power Input Bandwidth (FPBW)
Analog Input Common Mode Voltage Range (V
IN
+ + V
IN
-)/2
INTERNAL VOLTAGE REFERENCE
Reference Output Voltage, V
ROUT
Reference Output Current
Reference Temperature Coefficient
REFERENCE VOLTAGE INPUT
Reference Voltage Input, V
RIN
Total Reference Resistance, R
L
Reference Current
DC BIAS VOLTAGE
DC Bias Voltage Output, V
DC
Max Output Current (Not To Exceed)
DIGITAL INPUTS (CLK)
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic High Current, I
IH
Input Logic Low Current, I
IL
Input Capacitance, C
IN
DIGITAL OUTPUTS
(D0-D13)
Output Logic High Voltage, V
OH
Output Logic Low Voltage, V
OL
Output Capacitance, C
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
AP
Aperture Jitter, t
AJ
Data Output Delay, t
OD
Data Output Hold, t
H
Data Latency, t
LAT
Clock Pulse Width (Low)
Clock Pulse Width (High)
POWER SUPPLY CHARACTERISTICS
Total Supply Current, I
CC
Analog Supply Current, AI
CC
Digital Supply Current, DI
CC1
Output Supply Current, DI
CC2
Power Dissipation
Offset Error PSRR,
∆V
OS
Gain Error PSRR,
∆FSE
NOTES:
3.95
-
-
4.0
-
125
4.05
0.75
-
V
mA
ppm/
o
C
-
-
-
4.0
5.6
715
-
-
-
V
kΩ
µA
-
-
2.3
-
-
1
V
mA
2.0
-
V
CLK
= 5V
V
CLK
= 0V
-10.0
-10.0
-
-
-
-
-
10
-
0.8
+10.0
+10.0
-
V
V
µA
µA
pF
I
OH
= 100µA
I
OL
= 100µA
3.5
-
-
-
-
5
-
1.5
-
V
V
pF
-
-
-
(Note 2)
For a Valid Sample (Note 2)
5MSPS Clock (Note 2)
5MSPS Clock (Note 2)
5
-
95
95
7
1
50
8
-
100
100
-
-
60
-
4
105
105
ns
ps (RMS)
ns
ns
Cycles
ns
ns
V
IN
+ = V
IN
- = V
DC
V
IN
+ = V
IN
- = V
DC
V
IN
+ = V
IN
- = V
DC
V
IN
+ = V
IN
- = V
DC
V
IN
+ = V
IN
- = V
DC
AV
CC
or DV
CC
= 5V
±
5%
AV
CC
or DV
CC
= 5V
±
5%
-
-
-
-
-
-
-
70
50
14
6
350
2
45
80
-
-
-
400
-
-
mA
mA
mA
mA
mW
LSB
LSB
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
4
HI5905
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
S
N - 1
H
N - 1
S
N
H
N
S
N + 1
H
N + 1
S
N + 2
H
N + 2
S
N + 3
H
N + 3
S
N + 4
H
N + 4
S
N + 5
H
N + 5
S
N + 6
H
N + 6
INPUT
S/H
1ST
STAGE
B
1
,
N - 1
B
1, N
B
1, N + 1
B
1, N + 2
B
1, N + 3
B
1, N + 4
B
1, N + 5
2ND
STAGE
B
2
,
N - 2
B
2
,
N - 1
B
2
,
N
B
2
,
N + 1
B
2
,
N + 2
B
2
,
N + 3
B
2
,
N + 4
3RD
STAGE
4TH
STAGE
B
3
,
N - 2
B
3
,
N - 1
B
3
,
N
B
3
,
N + 1
B
3
,
N + 2
B
3
,
N + 3
B
3
,
N + 4
B
4
,
N - 3
B
4
,
N - 2
B
4
,
N - 1
B
4
,
N
B
4
,
N + 1
B
4
,
N + 2
B
4
,
N + 3
5TH
STAGE
B
5
,
N - 3
B
5
,
N - 2
B
5
,
N - 1
B
5
,
N
B
5
,
N + 1
B
5
,
N + 2
B
5
,
N + 3
DATA
OUTPUT
D
N - 4
D
N - 3
t
LAT
D
N - 2
D
N - 1
D
N
D
N + 1
D
N + 2
NOTES:
4. S
N
: N-th sampling period.
5. H
N
: N-th holding period.
6. B
M , N
: M-th stage digital output corresponding to N-th sampled
input.
7. D
N
: Final data output corresponding to N-th sampled input.
FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG
INPUT
t
AP
t
AJ
CLOCK
INPUT
1.5V
1.5V
t
OD
t
H
3.5V
DATA N-1
1.5V
DATA N
DATA
OUTPUT
FIGURE 2. INPUT-TO-OUTPUT TIMING
5
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