HB52F168GB-B
HB52D168GB-B
EO
Description
Features
128 MB Unbuffered SDRAM Micro DIMM
16-Mword
×
64-bit, 133/100 MHz Memory Bus, 1-Bank Module
(4 pcs of 16 M
×
16 components)
PC133/100 SDRAM
The HB52F168GB and HB52D168GB are a 16M
×
64
×
1 banks Synchronous Dynamic RAM Micro Dual
In-line Memory Module (Micro DIMM), mounted 4 pieces of 256-Mbit SDRAM (HM5225165BTT) sealed
in TSOP package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of
the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high
density mounting possible without surface mount technology. They provide common data inputs and outputs.
Decoupling capacitors are mounted beside TSOP on the module board.
•
144-pin Zig Zag Dual tabs socket type (dual lead out)
Outline: 38.00 mm (Length)
×
30.00 mm (Height)
×
3.80 mm (Thickness)
Lead pitch: 0.50 mm
•
3.3 V power supply
•
Clock frequency: 133/100 MHz (max)
•
LVTTL interface
•
Data bus width:
×
64 Non parity
•
Single pulsed
RAS
•
4 Banks can operates simultaneously and independently
•
Burst read/write operation and burst read/single write operation capability
•
Programmable burst length: 1/2/4/8
•
2 variations of burst sequence
Sequential
Interleave
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
L
Pr
E0008H10 (1st edition)
(Previous ADE-203-1219A (Z))
Jan. 19, 2001
od
uc
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HB52F168GB-B, HB52D168GB-B
•
•
•
•
Programmable
CE
latency: 2/3
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
Auto refresh
HB52F168GB-xxBL
HB52D168GB-xxBL
EO
Type No.
HB52F168GB-75B*
1
HB52F168GB-75BL*
1
HB52D168GB-A6B
HB52D168GB-A6BL
HB52D168GB-B6B*
2
HB52D168GB-B6BL*
2
Self refresh
•
Low self refresh current :
:
Ordering Information
Frequency
CE
latency
3
3
2/3
2/3
3
3
Package
Micro DIMM (144-pin)
Contact pad
Gold
Notes: 1. 100 MHz operation at
CE
latency = 2.
2. 66 MHz operation at
CE
latency = 2.
Pin Arrangement
L
133 MHz
133 MHz
100 MHz
100 MHz
100 MHz
100 MHz
Pr
Front Side
od
143pin
144pin
1pin
2pin
uc
t
Back Side
Data Sheet E0008H10
2
HB52F168GB-B, HB52D168GB-B
Front side
Pin No.
61
63
65
67
69
71
Signal name Pin No.
CK0
V
CC
133
135
137
139
141
143
Back side
Signal name Pin No.
DQ29
DQ30
DQ31
V
SS
SDA
V
CC
62
64
66
68
70
72
Signal name Pin No.
CKE0
V
CC
CE
NC
A12
NC
134
136
138
140
142
144
Signal name
DQ61
DQ62
DQ63
V
SS
SCL
V
CC
EO
RE
W
S0
NC
Pin Description
Pin name
A0 to A12
L
Function
Address input
Row address A0 to A12
Column address A0 to A8
Bank select address
Data-input/output
Pr
Chip select
Write enable
Byte input/output mask
Clock input
Clock enable
Power supply
Ground
No connection
Data Sheet E0008H10
BA0/BA1
DQ0 to DQ63
S0
RE
CE
W
DQMB0 to DQMB7
CK0/CK1
CKE0
SDA
SCL
V
CC
V
SS
NC
Row address asserted bank enable
Column address asserted
Data-input/output for serial PD
Clock input for serial PD
od
uc
t
4
HB52F168GB-B, HB52D168GB-B
Serial PD Matrix*
1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
80
08
04
0D
09
01
40
00
01
75
128
256 byte
SDRAM
13
9
1
64
0 (+)
LVTTL
CL = 3
EO
0
1
2
3
4
5
6
7
8
9
Memory type
10
(-A6/B6) 6 ns
11
12
13
14
15
SDRAM width
16
17
18
19
Number of bytes used by
module manufacturer
Total SPD memory size
Number of row addresses bits 0
Number of column addresses
bits
Number of banks
Module data width
0
0
0
Module data width (continued) 0
Module interface signal levels 0
SDRAM cycle time
(highest
CE
latency)
(-75) 7.5 ns
(-A6/B6) 10 ns
0
SDRAM access from Clock
(highest
CE
latency)
(-75) 5.4 ns
Module configuration type
Refresh rate/type
Error checking SDRAM width
0
SDRAM device attributes:
minimum clock delay for back-
to-back random column
addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes:
number of banks on SDRAM
device
SDRAM device attributes:
CE
latency
SDRAM device attributes:
S
latency
0
0
L
Pr
1
0
1
0
0
0
1
0
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Data Sheet E0008H10
0
0
0
0
0
A0
54
1
0
0
0
0
0
1
0
0
0
60
00
82
Non parity
Normal
(7.8125 µs)
Self refresh
×
16
—
1 CLK
od
0
0
0
0
0
0
10
00
0
0
1
01
1
1
1
0
1
0
0F
04
1
0
1
0
0
1
06
01
uc
1, 2, 4, 8
4
2, 3
0
t
5