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74LVX161284MTD

Description
17 LINE TRANSCEIVER, PDSO48
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size114KB,11 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74LVX161284MTD Overview

17 LINE TRANSCEIVER, PDSO48

74LVX161284MTD Parametric

Parameter NameAttribute value
Brand NameFairchild Semiconductor
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts48
Manufacturer packaging code48 LD,TSSOP,JEDEC MO-153, 6.1MM WIDE
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresCONTAINS EIGHT BIDIRECTIONAL DATA BUFFERS
Differential outputNO
Number of drives14
Input propertiesSCHMITT TRIGGER
Interface integrated circuit typeLINE TRANSCEIVER
Interface standardsIEEE 1284
JESD-30 codeR-PDSO-G48
JESD-609 codee3
length12.5 mm
Humidity sensitivity level2
Number of functions13
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum receive delay44 ns
Number of receiver bits13
Maximum seat height1.2 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
Supply voltage 1-max5.5 V
Mains voltage 1-minute3 V
Supply voltage1-Nom3.15 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
maximum transmission delay44 ns
width6.1 mm
Base Number Matches1
74LVX161284 Low Voltage IEEE 161284 Translating Transceiver
January 1999
Revised June 2005
74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
r
14 mA) and are connected to a
separate power supply pin (V
CC
-cable) to allow these out-
puts to be driven by a higher supply voltage than the A-
side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the V
CC
-cable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A
1
–A
8
/B
1
–B
8
transceiver
pins.
Features
s
Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s
Translation capability allows outputs on the cable side to
interface with 5V signals
s
All inputs have hysteresis to provide noise margin
s
B and Y output resistance optimized to drive external
cable
s
B and Y outputs in high impedance mode during power
down
s
Inputs and outputs on cable side have internal pull-up
resistors
s
Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
s
Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Order Number
74LVX161284MEA
74LVX161284MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
HD
DIR
A
1
–A
8
B
1
–B
8
A
9
–A
13
Y
9
–Y
13
A
14
–A
17
C
14
–C
17
PLH
IN
PLH
HLH
IN
HLH
Description
High Drive Enable Input (Active HIGH)
Direction Control Input
Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
Host Logic HIGH Input
Host Logic HIGH Output
© 2005 Fairchild Semiconductor Corporation
DS500202
www.fairchildsemi.com

74LVX161284MTD Related Products

74LVX161284MTD 74LVX161284 74LVX161284MEA
Description 17 LINE TRANSCEIVER, PDSO48 17 LINE TRANSCEIVER, PDSO48 17 LINE TRANSCEIVER, PDSO48
Input properties SCHMITT TRIGGER SCHMITT TRIGGER SCHMITT TRIGGER
Interface standards IEEE 1284 IEEE 1284 IEEE 1284
Number of functions 13 17 13
Number of terminals 48 48 48
Maximum operating temperature 85 °C 85 Cel 85 °C
Minimum operating temperature -40 °C -40 Cel -40 °C
Number of receiver bits 13 17 13
surface mount YES Yes YES
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL
Brand Name Fairchild Semiconductor - Fairchild Semiconductor
Is it lead-free? Lead free - Lead free
Is it Rohs certified? conform to - conform to
Maker Fairchild - Fairchild
Parts packaging code TSSOP - SSOP
package instruction TSSOP, - SSOP,
Contacts 48 - 48
Manufacturer packaging code 48 LD,TSSOP,JEDEC MO-153, 6.1MM WIDE - 48LD, SSOP, JEDEC MO-118, 7.6MM WIDE
Reach Compliance Code unknown - compliant
ECCN code EAR99 - EAR99
Differential output NO - NO
Number of drives 14 - 14
Interface integrated circuit type LINE TRANSCEIVER - LINE TRANSCEIVER
JESD-30 code R-PDSO-G48 - R-PDSO-G48
JESD-609 code e3 - e3
length 12.5 mm - 15.875 mm
Humidity sensitivity level 2 - 1
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code TSSOP - SSOP
Package shape RECTANGULAR - RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH - SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 - 260
Certification status Not Qualified - Not Qualified
Maximum receive delay 44 ns - 44 ns
Maximum seat height 1.2 mm - 2.74 mm
Maximum supply voltage 3.6 V - 3.6 V
Minimum supply voltage 3 V - 3 V
Nominal supply voltage 3.3 V - 3.3 V
Supply voltage 1-max 5.5 V - 5.5 V
Mains voltage 1-minute 3 V - 3 V
Supply voltage1-Nom 3.15 V - 3.3 V
technology CMOS - CMOS
Terminal surface Matte Tin (Sn) - Matte Tin (Sn)
Terminal pitch 0.5 mm - 0.635 mm
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED
maximum transmission delay 44 ns - 44 ns
width 6.1 mm - 7.495 mm
Base Number Matches 1 - 1

74LVX161284MTD Similar Products

Part Number Manufacturer Description
74LVX161284AMTD Rochester Electronics 12 LINE TRANSCEIVER, PDSO48, 6.10 MM, MO-153, TSSOP-48
74VHC161284MTD Rochester Electronics 13 LINE TRANSCEIVER, PDSO48, 6.10 MM, MO-153, TSSOP-48
74VHC161284MTDX Rochester Electronics 13 LINE TRANSCEIVER, PDSO48, 6.10 MM, MO-153, TSSOP-48
74LVX161284AMTX Rochester Electronics 12 LINE TRANSCEIVER, PDSO48, 6.10 MM, MO-153, TSSOP-48
74LVX161284MTDX Rochester Electronics Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48
74LVX161284MTD_NL Fairchild Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, LEAD FREE, MO-153, TSSOP-48
74VHC161284MTDX_NL Fairchild Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48
74LVX161284MTDX_NL Fairchild Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153, TSSOP-48
74LVX161284AMTDX Fairchild Line Transceiver, 12 Func, 13 Driver, 12 Rcvr, PDSO48, 6.10 MM, MO-153, TSSOP-48
SN74LV161284DGGR Texas Instruments(德州仪器) 逻辑类型:IEEE STD 1284 转换收发器 额外特性:-
74LVX161284MEA Fairchild 17 LINE TRANSCEIVER, PDSO48
74LV161284DGGRG4 Texas Instruments(德州仪器) Interface - Specialized 19B Bus Interface
74LVX161284MEAX_NL Fairchild Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 0.300 INCH, MO-118, SSOP-48
74LVX161284MEA_NL Fairchild Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48
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