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8MJ4-212.500AJIT

Description
Oscillator
CategoryPassive components    oscillator   
File Size128KB,5 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

8MJ4-212.500AJIT Overview

Oscillator

8MJ4-212.500AJIT Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codeunknown
PRELIMINARY
Integrated
Circuit
Systems, Inc.
V
DD
ICS8M
X
4
LVDS C
LOCK
O
SCILLATOR
nOUT
OUT
ICS8M
X
4
L
OW
J
ITTER
, H
IGH
F
REQUENCY
XTAL O
SCILLATOR
Stable, ultra low jitter, LVDS clock generation
For Gigabit Ethernet, Fibre Channel, PCI-Express™, other applications
Clock output frequencies from 75MHz to 750MHz
One differential LVDS clock output
Output Enable (OE) pin (high impedance – when low)
Small 6-pin 5mm x 7mm x 1.5mm SMT ceramic package
Low profile package allows back-side PCB mounting
Pb-free RoHS compliant (by default; no additional code required)
3.3V or 2.5V device power supply options
Commercial (0 to +70
O
C) and Industrial (-40 to +85
O
C) temperatures
Frequency stability of ±50ppm or ±100ppm
(including initial accuracy, operating temperature variation, supply voltage
variation, load variation, reflow drift, and aging for 10 years)
5
6
8Mx4
(Top View)
2
• Low phase jitter < 1 ps rms maximum (12kHz to 20MHz)
6-pin CERHERMETIC 5mm x 7mm x 1.5mm SMT
E
LECTRICAL
S
PECIFICATIONS
Unless stated otherwise, V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to +70°C (commercial), T
A
= -40°C to +80°C (industrial)
Specifications
Item
DC Characteristics
Power Supply
(V
DD
, GND pins) Power Supply Voltage
Power Supply Current
Current w/Output Disabled
Input Capacitance
Output Enable
(OE pin)
LVCMOS/LVTTL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Internal Pullup Resistor
Clock Output
Level
(OUT, nOUT)
LVDS
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
AC Characteristics
Output
Output Frequency Range
(OUT, nOUT)
Frequency Stability Error
Output Duty Cycle
Output Rise Time
Output Fall Time
Oscillator Star t-up Time
RMS Phase Jitter, Random
1
Jitter
Symbol
Min.
3.135
2.375
Typ.
3.3
2.5
83
<0.6
4
0.7 * V
DD
0.3 * V
DD
5
-150
51
350
50
1.25
150
75
Δ
f/f
O
odc
t
R
t
F
t
OSC
t
jit (Ø)
t
DS2
t
RS
2
Max.
3.465
2.625
Units
V
V
mA
mA
pF
V
V
µA
µA
mV
mV
V
mV
MHz
ppm p-p
ppm p-p
%
ps
ps
ms
ps rms
ps
ps
ps
ps
ps
All conditions
8MH4 & 8MK4
8MG4 & 8MJ4
20% to 80%
of V
OD
3.3V operation
Test Conditions
V
DD
I
DD
I
OED
C
IN
V
IH
V
IL
I
IH
I
IL
R
PULLUP
V
OD
Δ
V
OD
V
OS
Δ
V
OS
2.5V operation (8MJ4 and 8MK4 only)
OE = V
DD
OE = GND
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
100
Ω
termination between OUT and nOUT.
See Parameter Measurement Information.
750
±100
±50
50
600
600
10
<1
0.2
3
3
25
4
Includes frequency set, V
DD
, T
A
and
load variation, reflow drift, 10 yr. aging
See Output Duty Cycle Diagram
and Rise/Fall Time Diagram in
Parameter Measurement Information
Time at Min. V
DD
(3.135V or 2.375V) to be 0s
design target
Deterministic
Random,
σ
of random jitter
Root Mean Square,
σ
of total jitter distribution
Peak-to-Peak
Accumulated Jitter, n = 2 to 50,000 cycles
t
RMS2
t
P-P
t
acc
2
2
NOTE 1: Measured using an Aeroflex PN9500 with a 12kHz to 20MHz integration range. NOTE 2: Measured using a Wavecrest SIA-3000.
Supply Voltage & Frequency Accuracy
G=
H=
J=
K=
8Mx4AJ
3.3V / 3.3V
3.3V / 3.3V
2.5V / 3.3V
2.5V / 3.3V
±50 ppm
±100 ppm
±50 ppm
±100 ppm
The Preliminary Information presented herein represents a product in prototyping or pre-production. The
noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorpo-
rated (ICS) reserves the right to change any circuitry or specifications without notice.
www.icst.com/products/hiperclocks.html
1
GND
REV. B FEBRUARY 10, 2006
OE
NC
3
1
4
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