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PCA9515AD/G,118

Description
DUAL LINE TRANSCEIVER, PDSO8
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size191KB,20 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Related ProductsFound20parts with similar functions to PCA9515AD/G,118
Download Datasheet Parametric Compare View All

PCA9515AD/G,118 Overview

DUAL LINE TRANSCEIVER, PDSO8

PCA9515AD/G,118 Parametric

Parameter NameAttribute value
Source Url Status Check Date2013-06-14 00:00:00
Brand NameNXP Semiconduc
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeSOIC
package instructionPLASTIC, TSSOP-8
Contacts8
Manufacturer packaging codeSOT96-1
Reach Compliance Codeunknow
Differential outputNO
Number of drives2
Input propertiesSTANDARD
Interface integrated circuit typeLINE TRANSCEIVER
Interface standardsGENERAL PURPOSE
JESD-30 codeS-PDSO-G8
JESD-609 codee4
length3 mm
Number of functions2
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeSOP8,.25
Package shapeSQUARE
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply2.5/3.3 V
Certification statusNot Qualified
Maximum receive delay130 ns
Number of receiver bits2
Maximum seat height1.1 mm
Maximum supply voltage2.7 V
Minimum supply voltage2.3 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
maximum transmission delay130 ns
width3 mm
PCA9515A
I
2
C-bus repeater
Rev. 5 — 23 March 2012
Product data sheet
1. General description
The PCA9515A is a CMOS integrated circuit intended for application in I
2
C-bus and
SMBus systems.
While retaining all the operating modes and features of the I
2
C-bus system, it permits
extension of the I
2
C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus
enabling two buses of 400 pF.
The I
2
C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9515A enables the system designer to isolate two halves of a bus, thus
more devices or longer length can be accommodated. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the
100 kHz bus is isolated when 400 kHz operation of the other is required.
Two or more PCA9515As cannot be put in series.
The PCA9515A design does not
allow this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage
levels are used to avoid lock-up conditions between the input and the output. A ‘regular
LOW’ applied at the input of a PCA9515A will be propagated as a ‘buffered LOW’ with a
slightly higher value. When this ‘buffered LOW’ is applied to another PCA9515A,
PCA9516A or PCA9518/A in series, the second PCA9515A, PCA9516A or PCA9518/A
will not recognize it as a ‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again.
The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, PCA9514/A cannot be used in
series with the PCA9515A, PCA9516A or PCA9518/A, but can be used in series with
themselves since they use shifting instead of static offsets to avoid lock-up conditions.
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input
threshold of each internal buffer is set about 0.07 V lower, when the output is internally
driven LOW. This prevents a lock-up condition from occurring.
2. Features and benefits
2-channel, bidirectional buffer
I
2
C-bus and SMBus compatible
Active HIGH repeater enable input
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard-mode and Fast-mode I
2
C-bus devices and multiple masters
Powered-off high-impedance I
2
C-bus pins
Operating supply voltage range of 2.3 V to 3.6 V
5.5 V tolerant I
2
C-bus and enable pins

PCA9515AD/G,118 Related Products

PCA9515AD/G,118 PCA9515AD/G,112 IPP60R040C7
Description DUAL LINE TRANSCEIVER, PDSO8 DUAL LINE TRANSCEIVER, PDSO8 Metal Oxide Semiconductor Field Effect Transistor
Input properties STANDARD standard -
Interface standards GENERAL PURPOSE GENERAL PURPOSE -
Number of functions 2 2 -
Number of terminals 8 8 -
Maximum operating temperature 85 °C 85 Cel -
Minimum operating temperature -40 °C -40 Cel -
Number of receiver bits 2 2 -
surface mount YES Yes -
Temperature level INDUSTRIAL INDUSTRIAL -
Terminal form GULL WING GULL WING -
Terminal location DUAL pair -

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