MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5408A is 4,194,304-bit CMOS static RAM organized as
524,288-words by 8-bit, fabricated using high-performance
quadruple-polysilicon and double metal CMOS technology.
The use of thin film transistor (TFT) load cells and CMOS periphery
results in a high density and low power static RAM.
The
M5M5408A is designed for memory applications where the high
performance, high reliability, large storage, simple interfacing and
battery back-up are important design objectives.
The M5M5408A is offered in a 32-pin plastic small outline
package (SOP) and a 32-pin thin small outline package (TSOP),
providing high board level packing densities. Two types of TSOP
packages are available, M5M5408ATP(normal lead bend type
package) and M5M5408ART (reverse lead bend type package).
Using both two types makes it easy to design a printed circuit
board.
PIN CONFIGURATION (TOP VIEW)
FEATURES
Type
Access
time
(max)
M5M5408AFP,TP,RT-70L-I
M5M5408AFP,TP,RT-10L-I
70ns
100ns
90mA
(Vcc=5.5V)
M5M5408AFP,TP,RT-70LL-I
M5M5408AFP,TP,RT-10LL-I
70ns
100ns
40µA
(Vcc=5.5v)
Power supply current
Active
(max)
Stand-by
(max)
200µA
(Vcc=5.5v)
A
18 1
A
16 2
A
14 3
A
12 4
A
7 5
A
6 6
A
5 7
A
4 8
A
3 9
A
2 10
A
1 11
A
0 12
DQ
1 13
DQ
2 14
DQ
3 15
(0V)
GND
16
V
CC
(5V)
31
A
15
30
A
17
29
W
28
A
13
27
A
8
26
A
9
25
A
11
24
OE
23
A
10
22
S
21
DQ
8
20
DQ
7
19
DQ
6
18
DQ
5
17
DQ
4
32
Outline 32P2M-A(FP)
32P3Y-H(TP)
M5M5408AFP,TP
-I
(5V)
V
CC
32
31
30
1
2
3
• Single +5V power supply
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S
• Data retention supply voltage=+2.0V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
• Small stand-by current………………0.4µA(typ.)
• Package
M5M5408AFP : 32 pin 525 mil SOP
M5M5408ATP : 32 pin 400 mil TSOP(II)
M5M5408ART : 32 pin 400 mil TSOP(II)
A
15
A
17
W
A
13
A
8
A
9
A
11
OE
A
10
S
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
29
28
27
26
25
24
23
22
21
20
19
18
17
4
5
6
7
8
9
10
11
12
13
14
15
16
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
GND
(0V)
Outline 32P3Y-J(RT)
M5M5408ART
-I
APPLICATION
Small capacity memory units, IC card, Battery operating system,
asynchronous server system
MITSUBISHI
ELECTRIC
1
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5408A is determined by a
combination of the device control inputs S, W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
W or S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable OE directly controls the output stage. Setting the OE
at a high level,the output stage is in a high-impedance state,
and the data bus contention problem in the write cycle is
eliminated.
A read cycle is executed by setting W at a high level and
OE at a low level while S are in an active state(S=L).
When setting S at a high level, the chips are in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-impedance
state, allowing OR-tie with other chips and memory expansion
by S. The power supply current is reduced as low as the
stand-by current which is specified as Icc3 or Icc4, and the
memory data can be held at +2V power supply, enabling
battery back-up operation during power failure or power-down
operation in the non-selected mode.
FUNCTION TABLE
S
H
L
L
L
W
X
L
H
H
OE
X
X
L
H
Mode
Non selection
Write
Read
DQ
High-impedance
D
IN
D
OUT
High-impedance
Icc
Standby
Active
Active
Active
BLOCK DIAGRAM
A
7
A
6
A
10
A
11
A
9
A
8
A
13
A
17
A
15
5
6
23
25
26
27
28
30
31
ADDRESS INPUT BUFFER
13
14
ROW DECODER
OUTPUT BUFFER
AMP.
524288 WORDS
x 8 BITS
512 ROWS
x 128 COLUMNS
x 64 BLOCKS
15
17
18
19
20
21
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
ADDRESS INPUT
BUFFER
A
16
A
14
A
12
A
5
A
4
A
3
A
2
A
1
A
0
2
3
4
7
8
9
10
11
12
CLOCK
GENERATOR
DATA INPUT
BUFFER
A
18
1
COLUMN
DECODER
SENSE
29
BLOCK DECODER
ADDRESS INPUT
BUFFER
22
24
W
S
OE
V
CC
(3.3V)
32
16
GND
(0V)
MITSUBISHI
ELECTRIC
2
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
cc
V
I
V
O
P
d
T
opr
T
stg
*
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Conditions
Ratings
-0.3~ 7
-0.3
*
~ Vcc+0.3
0~Vcc
Units
V
V
V
mW
°C
°C
With respect to GND
Ta=25°C
700
-40 ~ 85
-65 ~150
-3.0V in case of AC (Pulse width
≤
30ns)
ELECTRICAL CHARACTERISTICS
(Ta= -40~85°C, Vcc=5V±10%, unless otherwise noted)
Symbol
V
IH
V
IL
V
OH
V
OL
I
I
I
O
I
CC1
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
Output leakage current
Active supply current
(AC,MOS level)
Active supply current
(AC,TTL level)
I
CC3
I
CC4
*
Conditions
Min
2.2
-0.3
*
2.4
Vcc-0.5
Limits
Typ
Max
Vcc+0.3
0.8
Units
V
V
V
I
OH
=-1mA
I
OH
=-0.1mA
I
OL
=2mA
V
I
=0~Vcc
S=V
IH
,OE=V
IH
,V
I/O
=0~Vcc
S≤0.2V
Other inputs≤ 0.2V or
≥Vcc-0.2V
Output-open (duty 100%)
S=V
IL
,W=V
IH
Other inputs=V
IH
or V
IL
Output-open (duty 100%)
S
≥Vcc-0.2V
Minimum
cycle
0.4
±1
±1
50
25
60
30
80
V
µA
µA
mA
1MHz
Minimum
cycle
30
90
mA
40
200
µA
µA
mA
I
CC2
1MHz
FP,VP,RT-L
Stand by supply current
Stand by supply current
FP,VP,RT-LL
Other inputs=0 ~Vcc
S=V
IH
,Other inputs=0 ~Vcc
1.0
40
3
-3.0V in case of AC (Pulse width
≤
30ns)
CAPACITANCE
(Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted)
Symbol
C
i
C
o
Parameter
Input capacitance (Ta=25°C )
Output capacitance (Ta=25°C )
Conditions
V
I
=GND, V
i
=25mVrms,f=1MHz
V
O
=GND, V
o
=25mVrms,f=1MHz
Min
Limits
Typ
Max
6
8
Units
pF
pF
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is Vcc=5V,Ta=25°C
Note 3: Ci, Co are periodically sampled and are not 100% tested.
MITSUBISHI
ELECTRIC
3
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
SWITCHING CHARACTERISTICS
(Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted)
READ CYCLE
Limits
Symbol
Parameter
M5M5408FP,TP,
RT-70L-I,-70LL-I
M5M5408FP,TP,
RT-10L-I,-10LL-I
Units
Min
Max
Min
100
Max
ns
100
100
50
35
35
ns
ns
ns
ns
ns
ns
ns
ns
t
CR
t
a
(A)
t
a
(S)
t
a
(OE)
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
v
(A)
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S high
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address
70
70
70
35
25
25
10
5
10
10
5
10
TIMING REQUIREMENTS
(Ta=-40~85°C, Vcc=5V±10%, unless otherwise noted)
WRITE CYCLE
Limits
Symbol
Parameter
M5M5408FP,TP, M5M5408FP,TP,
RT-70L-I,-70LL-I RT-10L-I,-10LL-I
Units
Min
Max Min
100
60
0
80
80
35
0
0
25
25
Max
ns
ns
ns
ns
ns
ns
ns
ns
35
35
ns
ns
ns
ns
t
CW
t
w
(W)
t
su
(A)
t
su
(S)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
Write cycle time
Write pulse width
Address set up time
70
50
0
60
60
30
0
0
t
su
(A-WH)
Address set up time with respect to W high
Chip select set up time
Data set up time
Data hold time
Write recovery time
Output disable time after W low
Output disable time after OE high
Output enable time after W high
Output enable time after OE low
5
5
5
5
MITSUBISHI
ELECTRIC
4
MITSUBISHI LSIs
M5M5408AFP,TP,RT-70L-I,-70LL-I,
-10L-I,-10LL-I
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
TIMING DIAGRAMS
Read cycle
A 0~18
ta
(A)
ta
(S)
(Note4)
ÅiNote4Åj
(Note4)
t
CR
tv
(A)
S
ta
(OE)
ten
(OE)
tdis
(S)
OE
(Note4)
(Note4)
ten
(S)
tdis
(OE)
DQ1~8
(Dout )
W="H" level
Write cycle
(W control mode)
t
CW
A 0~18
tsu
(S)
S
(Note4)
(Note4)
tsu
(A-WH)
OE
tsu
(A)
tw
(W)
trec
(W)
W
tsu
(D)
th
(D)
DQ1~8
(Din)
tdis
(W)
tdis
(OE)
DATA IN
STABLE
ten
(OE)
ten
(W)
DQ1~8
(Dout)
MITSUBISHI
ELECTRIC
5
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