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ZNBG3001Q16TA

Description
Analog Circuit, 1 Func, PDSO16, QSOP-16
CategoryAnalog mixed-signal IC    The signal circuit   
File Size205KB,9 Pages
ManufacturerZetex Semiconductors
Websitehttp://www.zetex.com/
Download Datasheet Parametric Compare View All

ZNBG3001Q16TA Overview

Analog Circuit, 1 Func, PDSO16, QSOP-16

ZNBG3001Q16TA Parametric

Parameter NameAttribute value
MakerZetex Semiconductors
package instructionSSOP,
Reach Compliance Codeunknow
Analog Integrated Circuits - Other TypesANALOG CIRCUIT
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length4.9 mm
Humidity sensitivity level1
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature-30 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)12 V
Minimum supply voltage (Vsup)5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
Temperature levelOTHER
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width3.9116 mm
FET BIAS CONTROLLER
ISSUE 1- AUGUST 1998
DEVICE DESCRIPTION
The ZNBG series of devices are designed to
meet the bias requirements of GaAs and
HEMT FETs commonly used in satellite
receiver LNBs, PMR, cellular telephones etc.
with a minimum of external components.
With the addition of two capacitors and a
resistor the devices provide drain voltage
and current control for 3 external grounded
source FETs, generating the regulated
negative rail required for FET gate biasing
whilst operating from a single supply. This
negative bias, at -3 volts, can also be used to
supply other external circuits.
The ZNBG3000/1 contains three bias stages.
A single resistor allows FET drain current to
be set to the desired level. The series also
offers the choice of drain voltage to be set
for the FETs, the ZNBG3000 gives 2.2 volts
drain whilst the ZNBG3001 gives 2 volts.
These devices are unconditionally stable
over the full working temperature with the
FETs in place, subject to the inclusion of the
recommended gate and drain capacitors.
These ensure RF stability and minimal
injected noise.
ZNBG3000
ZNBG3001
It is possible to use less than the devices full
complement of FET bias controls, unused
drain and gate connections can be left open
circuit without affecting operation of the
remaining bias circuits.
In order to protect the external FETs the
circuits have been designed to ensure that,
under any conditions including power
up/down transients, the gate drive from the
bias circuits cannot exceed the range -3.5V
to 0.7V. Furthermore if the negative rail
experiences a fault condition, such as
overload or short circuit, the drain supply to
the FETs will shut down avoiding excessive
current flow.
The ZNBG3000/1 are available in QSOP16
packages for the minimum in devices size.
Device operating temperature is -40 to 70°C
to suit a wide range of environmental
conditions.
FEATURES
APPLICATIONS
Provides bias for GaAs and HEMT FETs
Drives up to three FETs
Dynamic FET protection
Drain current set by external resistor
Regulated negative rail generator
requires only 2 external capacitors
Choice in drain voltage
Wide supply voltage range
QSOP surface mount package
Satellite receiver LNBs
Private mobile radio (PMR)
Cellular telephones
Single in single out C Band LNB
4-137

ZNBG3001Q16TA Related Products

ZNBG3001Q16TA UZNBG3001Q16 ZNBG3000Q16TA ZNBG3001Q16TC
Description Analog Circuit, 1 Func, PDSO16, QSOP-16 Analog Circuit, 1 Func, PDSO16, QSOP-16 Analog Circuit, 1 Func, PDSO16, QSOP-16 Analog Circuit, 1 Func, PDSO16, QSOP-16
Maker Zetex Semiconductors Zetex Semiconductors Zetex Semiconductors Zetex Semiconductors
package instruction SSOP, SSOP, SSOP, SSOP,
Reach Compliance Code unknow unknown unknown unknow
Analog Integrated Circuits - Other Types ANALOG CIRCUIT ANALOG CIRCUIT ANALOG CIRCUIT ANALOG CIRCUIT
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code e3 e3 e3 e3
length 4.9 mm 4.9 mm 4.9 mm 4.9 mm
Humidity sensitivity level 1 1 1 1
Number of functions 1 1 1 1
Number of terminals 16 16 16 16
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C
Minimum operating temperature -30 °C -30 °C -30 °C -30 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP SSOP SSOP SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260 260
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.75 mm 1.75 mm 1.75 mm 1.75 mm
Maximum supply voltage (Vsup) 12 V 12 V 12 V 12 V
Minimum supply voltage (Vsup) 5 V 5 V 5 V 5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V
surface mount YES YES YES YES
Temperature level OTHER OTHER OTHER OTHER
Terminal surface MATTE TIN Matte Tin (Sn) MATTE TIN MATTE TIN
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.635 mm 0.635 mm 0.635 mm 0.635 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 40 40 40 40
width 3.9116 mm 3.9116 mm 3.9116 mm 3.9116 mm

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