Very Low Power CMOS SRAM
32K X 8 bit
Green package materials are compliant to RoHS
BS62LV256
n
FEATURES
Ÿ
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Ÿ
Very low power consumption :
V
CC
= 3.0V Operation current : 25mA (Max.) at 70ns
1mA (Max.) at 1MHz
Standby current : 0.01uA(Typ.) at 25
O
C
V
CC
= 5.0V Operation current : 40mA (Max.) at 70ns
2mA (Max.) at 1MHz
Standby current : 0.4uA (Typ.) at 25
O
C
Ÿ
High speed access time :
-70
70ns(Max.) at V
CC
:
3.0~5.5V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE and OE options
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation
Ÿ
Data retention supply voltage as low as 1.5V
n
DESCRIPTION
The BS62LV256 is a high performance, very low power CMOS Static
Random Access Memory organized as 32,768 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.01uA and maximum access time of 70ns in 3.0V
operation.
Easy memory expansion is provided by an active LOW chip enable
(CE), and active LOW output enable (OE) and three-state output
drivers.
The BS62LV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV256 is available in DICE form, JEDEC standard 28 pin
330mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm TSOP
(normal type).
n
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS62LV256PA
BS62LV256SA
BS62LV256TA
Automotive
Grade
O
-40 C to +125
O
C
0.4uA
0.01uA
25uA
10uA
2mA
40mA
1mA
25mA
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Typ.)
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
1MHz
f
Max.
V
CC
=3.0V
1MHz
f
Max.
PDIP-28
SOP-28
TSOP-28
n
PIN CONFIGURATIONS
n
BLOCK DIAGRAM
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
•
BS62LV256PA
BS62LV256SA
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A5
A6
A7
A12
A14
A13
A8
A9
A11
Address
Input
Buffer
9
Row
Decoder
512
Memory Array
512X512
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
64
Column Decoder
6
CE
8
Column I/O
Write Driver
Sense Amp
8
Data
Output
Buffer
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BS62LV256TA
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
WE
OE
V
CC
GND
Control
Address Input Buffer
A4 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS62LV256A
1
Revision 2.5A
Sep.
2006
BS62LV256
n
PIN DESCRIPTIONS
Name
A0-A14 Address Input
CE Chip Enable Input
Function
These 15 address inputs select one of the 32,768 x 8-bit in the RAM
CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
There 8 bi-directional ports are used to read data from or write data into the RAM.
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
Ports
V
CC
GND
Power Supply
Ground
n
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
Write
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
I/O OPERATION
High Z
High Z
D
OUT
D
IN
V
CC
CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
NOTES: H means V
IH
; L means V
IL
; X means don’t care (Must be V
IH
or V
IL
state)
n
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
(1)
n
OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
to 7.0
-40 to +125
-60 to +150
1.0
20
RANG
Automotive
AMBIENT
TEMPERATURE
-40
O
C to + 125
O
C
V
CC
2.4V ~ 5.5V
C
C
O
n
CAPACITANCE
(1)
(T
A
= 25 C, f = 1.0MHz)
O
W
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
C
IN
C
IO
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
6
8
pF
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2.
–2.0V
in case of AC pulse width less than 30 ns.
R0201-BS62LV256A
1. This parameter is guaranteed and not 100% tested.
2
Revision 2.5A
Sep.
2006
BS62LV256
n
DC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +125 C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
I
CC1
I
CCSB
I
CCSB1
PARAMETER
Power Supply
O
O
TEST CONDITIONS
MIN.
2.4
-0.5
(2)
TYP.
(1)
--
MAX.
5.5
UNITS
V
Input Low Voltage
--
0.8
V
CC
+0.3
(3)
V
Input High Voltage
2.2
--
V
Input Leakage Current
V
IN
= 0V to V
CC
CE= V
IH
, or OE = V
IH
,
V
I/O
= 0V to V
CC
--
--
1
uA
Output Leakage Current
--
--
1
uA
Output Low Voltage
V
CC
= Max, I
OL
= 0.5mA
--
--
0.4
V
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current
–
TTL
V
CC
= Min, I
OH
= -0.5mA
CE = V
IL
,
I
DQ
= 0mA, f = F
MAX(4)
CE = V
IL
,
I
DQ
= 0mA, f = 1MHz
CE = V
IH
,
I
DQ
= 0mA
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
2.4
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0.01
0.4
--
25
40
1
2
1.0
2.0
10
25
V
mA
mA
mA
Standby Current
–
CMOS
CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
uA
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
n
DATA RETENTION CHARACTERISTICS (T
A
= -40 C to +125 C)
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
O
TEST CONDITIONS
CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE≧V
CC
-0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
MIN.
1.5
--
0
TYP.
(1)
--
0.01
--
--
MAX.
--
5.0
--
--
UNITS
V
uA
ns
ns
See Retention Waveform
t
RC (2)
1. V
CC
=1.5V, T
A
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
n
LOW V
CC
DATA RETENTION WAVEFORM (CE Controlled)
Data Retention Mode
V
DR
≧1.5V
V
CC
V
IH
V
CC
V
CC
t
CDR
CE≧V
CC
- 0.2V
t
R
V
IH
CE
R0201-BS62LV256A
3
Revision 2.5A
Sep.
2006
BS62LV256
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
n
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
Output Load
Others
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
=
100pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
→ ←
Rise Time :
1V/ns
→ ←
Fall Time :
1V/ns
1. Including jig and scope capacitance.
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +125 C)
READ CYCLE
JEDEC
PARAMETER
NAME
PARANETER
NAME
CYCLE TIME : 70ns
(V
CC
= 3.0~5.5V)
MIN.
TYP.
MAX.
70
--
--
--
10
10
--
--
10
--
--
--
--
--
--
--
--
--
--
70
70
35
--
--
35
30
--
O
O
DESCRIPTION
UNITS
t
AVAX
t
AVQX
t
E1LQV
t
GLQV
t
E1LQX
t
GLQX
t
E1HQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS62LV256A
4
Revision 2.5A
Sep.
2006
BS62LV256
n
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
t
OH
READ CYCLE 2
(1,3,4)
CE
t
ACS
t
CLZ
D
OUT
(5)
t
CHZ
(5)
READ CYCLE 3
(1, 4)
t
RC
ADDRESS
t
AA
OE
t
OE
CE
(5)
t
OH
t
OLZ
t
ACS
t
CLZ
t
OHZ
t
CHZ
(5)
(1,5)
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state with C
L
= 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV256A
5
Revision 2.5A
Sep.
2006
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