K7Q163682A-FC15 datasheet, PDF

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K7Q163682A-FC15: DescriptionQDR SRAM, 512KX36, 2.7ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165; Categorystorage storage; File Size504KB，17 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7Q163682A-FC15 Overview

QDR SRAM, 512KX36, 2.7ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

K7Q163682A-FC15 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compli
ECCN code	3A991.B.2.A
Maximum access time	2.7 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	150 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bi
Memory IC Type	QDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.21 A
Minimum standby current	1.7 V
Maximum slew rate	0.51 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm

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K7Q163682A

K7Q161882A

Document Title

512Kx36-bit, 1Mx18-bit QDR

SRAM

512Kx36 & 1Mx18 QDR

b2 SRAM

Revision History

Rev. No.

0.0

0.1

History

1. Initial document.

1. Icc, Isb addition

2. 1.8V Vddq addition

3. Speed bin change

1. Changed Pin configuration at x36 organization.

- 9F ; from Q14 to D14 .

- 10F ; from D14 to Q14 .

2. Reserved pin for high density name change from NC to Vss/SA

1. Final SPEC release

2. Modify thermal resistance

Draft Date

May, 22 2001

Remark

Advance

Sep,03 2001

Advance

0.2

Nov. 20. 2001

Preliminary

1.0

July, 03. 2002

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

-1-

July 2002

Rev 1.0

K7Q163682A

K7Q161882A

GENERAL DESCRIPTION

512Kx36 & 1Mx18 QDR

b2 SRAM

The K7Q163682A and K7Q161882A are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.

They are organized as 524,288 words by 36bits for K7Q163682A and 1,048,576 words by 18 bits for K7Q161882A.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports

with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram

on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.

And totally independent read and write ports eliminate the need for high speed bus turn around.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Read address is registered on rising edges of the input K clocks, and write address is

registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.

Synchronous pipeline read and early write enable high speed operations.

Simple depth expansion is accomplished by using R and W for port selection.

Byte write operation is supported with BW

and BW

( BW

and BW

3 )

pins.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7Q163682A and K7Q161882A are implemented with SAMSUNG's high performance 6T CMOS technology and is available

in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initiated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K instead of C and C.

When the R is disabled after a read operation, the K7Q163682A and K7Q161882A will first complete burst read operation

before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

-5-

July 2002

Rev 1.0

K7Q163682A-FC15 Related Products

	K7Q163682A-FC15	K7Q161882A-FC10	K7Q161882A-FC13	K7Q161882A-FC15	K7Q163682A-FC13	K7Q163682A-FC10
Description	QDR SRAM, 512KX36, 2.7ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	QDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	QDR SRAM, 1MX18, 3ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	QDR SRAM, 1MX18, 2.7ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	QDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	QDR SRAM, 512KX36, 3ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40
Contacts	165	165	165	165	165	165
Reach Compliance Code	compli	compliant	compliant	compliant	compliant	compli
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	2.7 ns	3 ns	3 ns	-	3 ns	3 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	150 MHz	100 MHz	133 MHz	-	133 MHz	100 MHz
I/O type	SEPARATE	SEPARATE	SEPARATE	-	SEPARATE	SEPARATE
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	-	R-PBGA-B165	R-PBGA-B165
JESD-609 code	e0	e0	e0	-	e0	e0
length	15 mm	15 mm	15 mm	-	15 mm	15 mm
memory density	18874368 bi	18874368 bit	18874368 bit	-	18874368 bit	18874368 bi
Memory IC Type	QDR SRAM	QDR SRAM	QDR SRAM	-	QDR SRAM	QDR SRAM
memory width	36	18	18	-	36	36
Number of functions	1	1	1	-	1	1
Number of terminals	165	165	165	-	165	165
word count	524288 words	1048576 words	1048576 words	-	524288 words	524288 words
character code	512000	1000000	1000000	-	512000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	-	70 °C	70 °C
organize	512KX36	1MX18	1MX18	-	512KX36	512KX36
Output characteristics	3-STATE	3-STATE	3-STATE	-	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	-	LBGA	LBGA
Encapsulate equivalent code	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	-	BGA165,11X15,40	BGA165,11X15,40
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	-	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	-	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
power supply	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V	-	1.5/1.8,1.8 V	1.5/1.8,1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.4 mm	1.4 mm	-	1.4 mm	1.4 mm
Maximum standby current	0.21 A	0.19 A	0.2 A	-	0.2 A	0.19 A
Minimum standby current	1.7 V	1.7 V	1.7 V	-	1.7 V	1.7 V
Maximum slew rate	0.51 mA	0.39 mA	0.44 mA	-	0.47 mA	0.42 mA
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	-	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	-	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	-	1.8 V	1.8 V
surface mount	YES	YES	YES	-	YES	YES
technology	CMOS	CMOS	CMOS	-	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	-	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	-	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
width	13 mm	13 mm	13 mm	-	13 mm	13 mm

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