3.3V and 5V TTL, Low Jitter PLL Module with Internal VCXO
SCR050 Product Brief
Description
The SCR050 series offers a versatile PLL solution with an
embedded high-performance VCXO for use in networking and
telecommunications applications. The SCR050 module performs
clock recovery and data retiming (CDR), jitter filtering of an
input clock signal, or frequency translation to meet the specific
requirements of a given application.
Features
▪ Integrated PLL with quartz-stabilized VCXO
▪ User-defined PLL loop response
▪ Input data rates from 8 kbps to 65 kbps, TTL compatible
▪ Two-frequency output with Tri-state control
▪ Recovered clock & data outputs, TTL compatible
▪ NRZ data compatible
▪ Loss of Signal (LOS) status alarm with automatic free-run
switching
▪ Input control for forced free-run operating mode
▪ Rugged, shielded FR4 package available in thru-hole and true
SMD
Applications
▪ CDR for T1/E1 and T3/E3 equipment
▪ CDR for video distribution systems
▪ CDR for telemetric/satellite systems
▪ Frequency translation (step-up) of a reference signal for
synchronous applications
▪ Jitter filtering of a distributed or recovered clock signal
Functional Block Diagram
CLK IN
DATA IN
The SCR050 device combines flexible IC functionality from
Pericom® with high-performance fundamental-mode quartz
VCXO technology from SaRonix™ into a single, modular
solution for ultra-low output jitter and fast acquisition of the
data/clock inputs. The TTL-compatible device features a user-
configurable loop filter to fine-tune the PLL response for the
particular application, output disable controls, and a Loss of
Signal (LOS) alarm.
Owing to unique invention, the SCR050 is an RFI-shielded
modular design set on an FR4 base, available with true SMD pads
or a molded leadframe, and featuring a body thickness less than
3.5mm. The SCR050 solution is mechanically interchangeable
and socket-compatible with similar devices available on the
market.
Performance Features
Parameter
Input data rate (NRZ)
Input data rate (RZ)
Operating Frequency
(CLK1)
Operating Frequency
(CLK2)
Free-Run Accuracy
Specification
8 kbps to 65.536 Mbps
8 kbps to 32.768 Mbps
12 to 65.536 MHz (as specified)
0.05 to 32.768 MHz (as specified)
+/-20 ppM through +/-100 ppM max (as specified)
over all conditions including operating
temperature, calibration tolerance, rated input
(supply) voltage, load changes, aging*, shock and
vibration
10 years @ 40°C average ambient operating
temperature
0 to +70°C or –40 to +85°C (as specified)
+/-20 ppM through +/-100 ppM min (as specified)
15ms typ
3.3V or 5V (7V absolute max) (as specified)
TTL compatible, 5 TTL load
5ns max (measured between 0.5 and 2.5V)
> 50dB (RDATA, RCLK)
< 0.001 UI (when locked to input)
0.7ps RMS (1-sigma) max, 12kHz to 40MHz
frequency band (free run mode)
LOSIN
HIZ
Phase Detector
& LOS Circuit
RCLK
RDAT A
LOS
PHO
CLK1
*Aging:
Operating Range
Track and hold range
Input Lock Acquisition
Time
Supply Voltage
Output Logic
Rise/Fall Time
Jitter attenuation
Jitter generation
Phase (computed) jitter
VC
OPP
OPN
OpA
÷N
CLK2
OPOUT
PB-249
Rev A.1
www.saronix.com
3.3V and 5V TTL, Low Jitter PLL Module with Internal VCXO
SCR050 Product Brief
Package Diagrams
Pin Description
Pin Name
VC
10.16
.400
Description
Control voltage for internal low-jitter VCXO
Negative input terminal to internal operational amplifier
Output terminal of internal operational amplifier
Positive input terminal to internal operational amplifier
TTL input. Logic 1 disables VC and internal VCXO reverts to nominal frequency (free-run,
stability as specified). Logic 0 or NC enables VC and internal VCXO for acquisition. LOSIN
is pulled-down internally.
Output signal of phase detector
TTL input. Input data stream to phase detector (NRZ compatible)
Circuit and case ground
TTL input. Input clock signal to phase detector
TTL output. Logic 1 upon 256 consecutive transition-free DATAIN bits. Logic 0 upon first
transition
TTL output. Recovered clock, jitter-attenuated
TTL output. Recovered data stream, retimed with RCLK
TTL output. A binary quotient of CLK1 (as specified)
TTL input. Logic 0 disables all clock and data outputs to Hi-Z. Logic 1 or NC activates all
outputs
TTL output. Output clock of internal low-jitter VCXO (as specified)
Supply voltage (as specified)
OPN
OPOUT
OPP
LOSIN
20.32
.800
4.15
.163
PHO
2.54
.100
1
2
3
4
5
6
7
8
6.70 10.16
.263 .400
1.73
.068
16
15
14
13
12
11
10
9
DATAIN
GND
CLKIN
LOS
RCLK
20.32
.800
1.2
0.47
RDATA
CLK2
HIZ
CLK1
VDD
S Package w/ Surface Mount
#12 RDATA
#15 OUT1
#13 OUT2
#16 VCC
#11 RCLK
#14 HIZ
#9 CLKIN
7.78±0.25
.310±.010
#10 LOS
Part Numbering Guide
SCR050 S A A A A - 032.7680/016.3840(T)
SaRonix Clock Recovery Model
Package Type
S: Surface Mount
T: Thru Hole DIP
CLK2 Divide
A: /2 F: /64
B: /4 G: /128
C: /8 H: /256
D: /16 K: disabled
E: /32
Temp. Range &
Free Run Accuracy
AA: ±20ppM, 0~70ºC
A: ±25ppM, 0~70ºC
B: ±50ppM, 0~70ºC
C: ±100ppM, 0~70ºC (std)
E: ±50ppM,-40º~85ºC
H: ±32ppM, -40º~85ºC
T: ±100ppM, -40º~85ºC (std)
CLK2 Freq (MHz)
CLK1 Freq MHz)
Absolute Pull Range:
C: ±20ppM
F: ±32ppM
G: ±50ppM
H: ±100ppM
Packaging
(T) = Tape & Reel
SMD only
Blank = Bulk
Supply Voltage
A: 5.0V
3: 3.3V
#3 OPOUT
#4 OPP
#7 DATAIN
#1 V/C
#2 OPN
#5 LOSIN
20.32±0.20
.800±.008
#16 PHO
#9 GND
3.55 max
1.40
3.52±0.25
.139±.010
0.46±0.05
0.18±.002
0.88
.034
2.54
.100
17.78
.700
1.17±0.05
.046±.002
T Package with Thru Hole DIP
About SaRonix
SaRonix, Inc is a wholly owned subsidiary of Pericom Semiconductor Corporation.
Since 1975, SaRonix has specialized in high-performance frequency control products.
Today, Pericom and SaRonix combine advanced quartz oscillator technologies with
flexible silicon IC solutions and other discrete devices to deliver a range of integrated
modular timing solutions for telecommunications, datacom, storage fabric, and wireless
applications.
PB-249
Rev A.1
www.saronix.com
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