HV20220
Low Charge Injection,
8-Channel, High Voltage Analog Switches
Features
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HVCMOS
®
technology for high performance
Very low quiescent power dissipation (-10µA)
Output on-resistance typically 22Ω
Low parasitic capacitances
DC to 50MHz small signal frequency response
-60dB typical output off isolation at 5.0MHz
CMOS logic circuitry for low power
Excellent noise immunity
On-chip shift register, latch and clear logic circuitry
Flexible high voltage supplies
General Description
This device is a low charge injection, 8-channel, high-voltage
analog switch integrated circuit (IC) intended for use in appli-
cations requiring high voltage switching controlled by low volt-
age control signals, such as ultrasound imaging and printers.
Input data is shifted into an 8-bit shift register which can then
be retained in an 8-bit latch. To reduce any possible clock
feed-through noise, Latch Enable Bar (LE) should be left high
until all bits are clocked in. Using HVCMOS
®
technology, this
switch combines high voltage bilateral DMOS switches and
low power CMOS logic to provide efficient control of high volt-
age analog signals.
These ICs are suitable for various combinations of high volt-
age supplies, e.g., V
PP
/V
NN
: +50V/-150V, or +100V/-100V.
Applications
►
Medical ultrasound imaging
►
Piezoelectric transducer drivers
Block Diagram
LATCHES
DIN
LEVEL
SHIFTERS
OUTPUT
SWITCHES
SW0
D
LE
CL
D
LE
CL
CLK
SW1
D
LE
CL
SW2
8-Bit
Shift
Register
D
LE
CL
SW3
D
LE
CL
SW4
D
LE
CL
SW5
DOUT
D
LE
CL
SW6
D
LE
CL
SW7
VDD
LE
CL
VNN
VPP
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
HV20220
Ordering Information
Package Options
Device
7.00x7.00mm body
1.60mm height (max)
0.50mm pitch
48-Lead LQFP
.453x.453in body
.180in height (max)
.050in pitch
28-Lead PLCC
HV20220
HV20220FG-G
HV20220PJ-G
-G indicates the part is RoHS compliant (Green)
Absolute Maximum Ratings
Parameter
V
DD
logic power supply voltage
V
PP
- V
NN
supply voltage
V
PP
positive high voltage supply
V
NN
negative high voltage supply
Logic input voltages
Analog signal range
Peak analog signal current/channel
Storage temperature
Power dissipation:
48-Lead LQFP
28-JLead PLCC
Value
-0.5V to +15V
220V
-0.5V to V
NN
+200V
+0.5V to -200V
-0.5V to V
DD
+0.3V
V
NN
to V
PP
3.0A
-65
O
C to +150
O
C
1.0W
1.2W
Pin Configurations
1
48
48-Lead LQFP (FG)
4
1 28
26
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
28-Lead PLCC (PJ)
Product Marking
Top Marking
YYWW
Operating Conditions
Sym
V
DD
V
PP
V
NN
V
IH
V
IL
V
SIG
T
A
Parameter
Logic power supply voltage
1,3
Value
4.5V to 13.2V
40V to V
NN
+200V
-40V to -160V
V
DD
-1.5V to V
DD
0V to 1.5V
V
NN
+10V to
V
PP
-10V
2
0 C to 70 C
O
O
HV20220FG
LLLLLLLLL
Positive high voltage supply
1,3
Negative high voltage supply
1,3
High level input voltage
Low-level input voltage
Analog signal voltage peak-to-peak
Operating free air temperature
Bottom Marking
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Package may or may not include the following marks: Si or
48-Lead LQFP (FG)
YY = Year Sealed
WW = Week Sealed
HV20220PJ
LLLLLLLLLL
L = Lot Number
C = Country of Origin*
Bottom Marking
A = Assembler ID*
= “Green” Packaging
CCCCCCCCCCC
YYWW
Top Marking
Notes:
1. Power up/down sequence is arbitrary except GND must be powered-up first
and powered-down last.
2. V
SIG
must be V
NN
≤ V
SIG
≤ V
PP
or floating during power-up/down transition.
3. Rise and fall times of power supplies V
DD
, V
PP
, and V
NN
should not be less
than 1.0msec.
AAA
*May be part of top marking
Package may or may not include the following marks: Si or
28-Lead PLCC (PJ)
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
HV20220
DC Electrical Characteristics
Sym
Parameter
(Over operating conditions unless otherwise specified )
0
O
C
Min
-
-
Max
30
25
25
18
23
22
20
-
5.0
300
500
-
-
-
-
3.0
-
6.5
4.0
4.0
6.5
4.0
4.0
4.0
10
-
-
10
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.45
0.45
-
+25
O
C
Typ
26
22
22
18
20
16
5.0
15
1.0
100
100
10
-10
10
-10
3.0
-
-
-
-
-
-
-
-
-
0.70
0.70
-
Max
38
27
27
24
25
25
20
-
10
300
500
50
-50
50
-50
2.0
50
7.0
5.0
5.0
7.0
5.0
5.0
4.0
10
-
-
10
+70
O
C
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.40
0.40
-
Max
48
32
30
27
30
27
20
-
15
300
500
-
-
-
-
2.0
-
8.0
5.5
5.5
8.0
5.5
5.5
4.0
10
-
-
10
Units
Conditions
I
SIG
= 5.0mA
I
SIG
= 200mA
I
SIG
= 5.0mA
I
SIG
= 200mA
I
SIG
= 5.0mA
I
SIG
= 200mA
V
PP
= +40V
V
NN
= -160V
V
PP
= +100V
V
NN
= -100V
V
PP
= +160V
V
NN
= -40V
R
ONS
Small signal switch on-resistance
-
-
-
-
Ω
ΔR
ONS
R
ONL
I
SOL
V
OS
I
PPQ
I
NNQ
I
PPQ
I
NNQ
I
SW
f
SW
Small signal switch
on-resistance matching
Large signal switch on-resistance
Switch off leakage per switch
DC offset switch off
DC offset switch on
Quiescent V
PP
supply current
Quiescent V
NN
supply current
Quiescent V
PP
supply current
Quiescent V
NN
supply current
Switch output peak current
Output switching frequency
-
-
-
-
-
-
-
-
-
-
-
-
%
Ω
μA
mV
mV
μA
μA
μA
μA
A
kHz
I
SIG
= 5.0mA, V
PP
= +100V,
V
NN
= -100V
V
SIG
= V
PP
-10V, I
SIG
= 1.0A
V
SIG
= V
PP
-10V, V
NN
+10V
R
L
= 100kΩ
R
L
= 100kΩ
All switches off
All switches off
All switches on, I
SW
= 5.0mA
All switches on, I
SW
= 5.0mA
V
SIG
duty cycly < 0.1%
Duty cycle = 50%
V
PP
= +40V
V
NN
= -160V
All output
switches are
turning On
and Off at
50kHz with no
load
I
PP
Supply current
-
-
-
mA
V
PP
= +100V
V
NN
= -100V
V
PP
= +160V
V
NN
= -40V
V
PP
= +40V
V
NN
= -160V
I
NN
Supply curent
-
-
mA
V
PP
= +100V
V
NN
= -100V
V
PP
= +160V
V
NN
= -40V
All output
switches are
turning On
and Off at
50kHz with no
load
I
DD
I
DDQ
I
SOR
I
SINK
C
IN
Logic supply average current
Logic supply quiescent current
Data out source current
Data out sink current
Logic input capacitance
-
-
0.45
0.45
-
mA
μA
mA
mA
pF
f
CLK
= 5.0MHz, V
DD
= 5.0V
---
V
OUT
= V
DD
-0.7V
V
OUT
= 0.7V
---
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
HV20220
AC Electrical Characteristics
Sym
t
SD
t
WLE
t
DO
t
WCL
t
SU
t
H
f
CLK
t
R
, t
F
t
ON
t
OFF
dv/dt
Parameter
Set up time before LE rises
Time width of LE
Clock delay time to data out
Time width of CL
Set up time data to clock
Hold time data from clock
Clock frequency
Clock rise and fall times
Turn on time
Turn off time
(Over recommended operating conditions: V
DD
= 5.0V, unless otherwise specified)
0
O
C
Min
150
150
-
150
15
35
-
-
-
-
-
Max
-
-
150
-
-
-
5.0
50
5.0
5.0
20
20
20
-
-
-
300
17
50
-
-
-
-
-
-
-
-
-
Min
150
150
-
150
15
35
-
-
-
-
-
-
-
-30
-58
-60
-
5.0
25
-
-
-
-
-
-
-
-
-
+25
O
C
Typ
-
-
-
-
8.0
-
-
-
-
-
-
-
-
-33
-
-70
-
12
38
-
-
-
-
-
-
820
600
350
Max
-
-
150
-
-
-
5.0
50
5.0
5.0
20
20
20
-
-
-
300
17
50
150
150
150
150
150
150
-
-
-
+70
O
C
Min
150
150
-
150
20
35
-
-
-
-
-
-
-
-30
-58
-60
-
5.0
25
-
-
-
-
-
-
-
-
-
Max
-
-
150
-
-
-
5.0
50
5.0
5.0
20
20
20
-
-
-
300
17
50
-
-
-
-
-
-
-
-
-
Units Conditions
ns
ns
ns
ns
ns
ns
MHz
ns
μs
μs
---
---
---
---
---
---
50% Duty cycle, f
DATA
= f
CLK
/2
---
V
SIG
= V
PP
-10V, R
LOAD
= 10kΩ
V
SIG
= V
PP
-10V, R
LOAD
= 10kΩ
V
PP
= +160V, V
NN
= -40V
V/ns
V
PP
= +100V, V
NN
= -100V
V
PP
= +40V, V
NN
= -160V
dB
dB
mA
pF
pF
f = 5.0MHz, 1.0kΩ/15pF load
f = 5.0MHz, 50Ω load
f = 5.0MHz, 50Ω load
300ns pulse width,
2.0% duty cycle
0V, f = 1.0MHz
0V, f = 1.0MHz
V
PP
= +40V, V
NN
= -160V,
R
LOAD
= 50Ω
mV
V
PP
= +100V, V
NN
= -100V,
R
LOAD
= 50Ω
V
PP
= +160V, V
NN
= -40V,
R
LOAD
= 50Ω
V
PP
= +40V, V
NN
= -160V,
V
SIG
= 0V
pC
V
PP
= +100V, V
NN
= -100V,
V
SIG
= 0V
V
PP
= +160V, V
NN
= -40V,
V
SIG
= 0V
Maximun V
SIG
slew rate
-
-
K
O
K
CR
I
ID
Off isolation
Switch crosstalk
Output switch isolation diode
current
On capacitance SW to GND
-30
-58
-60
-
5.0
25
-
-
C
SG(OFF)
Off capacitance SW to GND
C
SG(ON)
+V
SPK
-V
SPK
+V
SPK
-V
SPK
+V
SPK
-V
SPK
Output voltage spike
-
-
-
-
-
QC
Charge injection
-
-
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
4
HV20220
Truth Table
D0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
Notes:
1.
2.
3.
4.
5.
6.
D1
D2
D3
D4
D5
D6
D7
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CLR
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
SW0
Off
On
SW1
SW2
SW3
SW4
SW5
SW6
SW7
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Hold Previous State
All Switches Off
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The eight switches operate independently.
Serial data is clocked in on the L to H transition of the CLK.
The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
D
OUT
is high when data in the shift register 7 is high.
Shift register clocking has no effect on the switch states if LE is high.
The CLR clear input overrides all other inputs.
Logic Timing Waveforms
DATA
IN
LE
D
N+1
50%
D
N
50%
D
N-1
50%
50%
t
WLE
t
SD
CLOCK
50%
t
SU
SU
t
h
50%
t
DD
DATA
OUT
V
OUT
OFF
(TYP)
50%
t
OFF
90%
t
ON
ON
50%
50%
10%
CLR
t
WCL
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
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