2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. D
OUT
is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
The previous articles (starting from i.MX6ULL Embedded Linux Development 1-Preliminary Exploration of Uboot Transplantation ) introduced the system transplantation of embedded Linux (Uboot, kernel and...
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introduction
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ARM Technology
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