VLSI CADI-Theory

A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc.  How do we design these complex chips?  Answer: CAD software tools.  Learn how to build thesA modern VLSI chip is a remarkably complex beast:  billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks).  How do people manage to design these complicated chips?  Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs.  This is the first step of the design chain, as we move from logic to layout.    Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level).

Recommended Background

Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms).  An understanding of basic digital design:  Boolean algebra, Kmaps, gates and flip flops, finite state machine design.  Linear algebra and calculus at the level of a junior or senior in engineering.  Exposure to basic VLSI at an undergraduate level is nice -- but it’s not necessary.  We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class.

How do people design these complex chips? Answer: A series of computer-aided design (CAD) tools provide an abstract description of the chip and gradually refine it to the final design. This course focuses on the main design tools used when building application-specific integrated circuit (ASIC) or system-on-chip (SoC) designs.

• Chapter 1：Welcome and Introduction (24 minutes and 59 seconds)

• Chapter 2：Computational Boolean Algebra_ Basics (15 minutes and 7 seconds)

• Chapter 3：Computational Boolean Algebra_ Boolean Difference (15 minutes and 51 seconds)

• Chapter 4：Computational Boolean Algebra_ Quantification Operators (13 minutes and 7 seconds)

• Chapter 5：Computational Boolean Algebra_ Application to Logic Network Repair (16 minutes and 19 seconds)

• Chapter 6：Computational Boolean Algebra_ Recursive Tautology (9 minutes and 48 seconds)

• Chapter 7：Computational Boolean Algebra_ Recursive Tautology—URP Implementation (20 minutes and 49 seconds)

• Chapter 8：BDD Basics, Part 1 (15 minutes and 17 seconds)

• Chapter 9：BDD Basics, Part 2 (16 minutes and 51 seconds)

• Chapter 10：BDD Sharing (17 minutes and 0 seconds)

• Chapter 11：BDD Ordering (28 minutes and 12 seconds)

• Chapter 12：Satisfiability (SAT), Part 1 (13 minutes and 51 seconds)

• Chapter 13：Boolean Constraint Propagation (BCP) for SAT (17 minutes and 56 seconds)

• Chapter 14：Using SAT for Logic (25 minutes and 45 seconds)

• Chapter 15：Level Logic_ Basics (9 minutes and 29 seconds)

• Chapter 16：Level Logic_ The Reduce-Expand-Irredundant Optimization Loop (13 minutes and 6 seconds)

• Chapter 17：Level Logic_ Details for One Step_ Expand (20 minutes and 33 seconds)

• Chapter 18：Multilevel Logic and the Boolean Network Model (13 minutes and 57 seconds)

• Chapter 19：Multilevel Logic_ Algebraic Model for Factoring (14 minutes and 15 seconds)

• Chapter 20：Multilevel Logic_ Algebraic Division (14 minutes and 13 seconds)

• Chapter 21：Multilevel Logic_ Role of Kernels and Co-Kernels in Factoring (14 minutes and 49 seconds)

• Chapter 22：Multilevel Logic_ Finding the Kernels (18 minutes and 28 seconds)

• Chapter 23：Mulitlevel Logic and Divisor Extraction—Single Cube Case (14 minutes and 24 seconds)

• Chapter 24：Mulitlevel Logic and Divisor Extraction—Multiple Cube Case (20 minutes and 38 seconds)

• Chapter 25：Multilevel Logic and Divisor Extraction—Finding Prime Rectangles & Summary (10 minutes and 46 seconds)

• Chapter 26：Multilevel Logic—Implicit Don’t Cares, Part 1 (17 minutes and 42 seconds)

• Chapter 27：Multilevel Logic—Implicit Don’t Cares, Part 2 (11 minutes and 18 seconds)

• Chapter 28：Multilevel Logic—Satisfiability Don’t Cares (10 minutes and 50 seconds)

• Chapter 29：Multilevel Logic—Controllability Don’t Cares (19 minutes and 59 seconds)

• Chapter 30：Multilevel Logic—Observability Don’t Cares (17 minutes and 22 seconds)