• You can log in to your eeworld account to continue watching:
  • Multilevel Logic_ Algebraic Division
  • Login
  • Duration:14 minutes and 13 seconds
  • Date:2021/08/15
  • Uploader:木犯001号
Introduction
keywords: integrated circuit
A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc.  How do we design these complex chips?  Answer: CAD software tools.  Learn how to build thesA modern VLSI chip is a remarkably complex beast:  billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks).  How do people manage to design these complicated chips?  Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs.  This is the first step of the design chain, as we move from logic to layout.    Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level).

Recommended Background

Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms).  An understanding of basic digital design:  Boolean algebra, Kmaps, gates and flip flops, finite state machine design.  Linear algebra and calculus at the level of a junior or senior in engineering.  Exposure to basic VLSI at an undergraduate level is nice -- but it’s not necessary.  We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class.

How do people design these complex chips? Answer: A series of computer-aided design (CAD) tools provide an abstract description of the chip and gradually refine it to the final design. This course focuses on the main design tools used when building application-specific integrated circuit (ASIC) or system-on-chip (SoC) designs.

Unfold ↓

You Might Like

Recommended Posts

cpld learning program
[i=s] This post was last edited by paulhyde on 2014-9-15 09:22 [/i] cpld learning
220314 Electronics Design Contest
Request angle sensor information
[i=s]This post was last edited by paulhyde on 2014-9-15 08:54[/i] Angle sensor information! ! ! !
a271543008 Electronics Design Contest
What is the difference between NFC and RFID?
[size=4] NFC and RFID are both technologies that have received much attention in recent years. They have similarities, but more importantly, they are different, such as technical principles and applic
Jacktang RF/Wirelessly
High score seeking mentor graphics software
Mentor Graphics If you have any, can you please send them to me? If I receive the software, I will give you extra points.
helly0917 Embedded System
About nuclues net!
If my network chip is an I/O Port Device, how do I know that the protocol stack has packets to send? More specifically, how does my NUCLEUS NET interface with the sender program of my driver? Please h
SPEED Embedded System

Recommended Content

Hot ArticlesMore

可能感兴趣器件

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号