The circuit shown in Figure 1 is a fully isolated 12-bit, 300 kSPS data acquisition system using only three active devices.

The system operates from a single 3.3 V supply and can handle ±10 V input signals. After room temperature calibration, the total error does not exceed ±0.1% FSR over a temperature variation of ±10°C, making it ideal for a variety of industrial measurement applications.

The circuit's small size makes the combination an industry-leading solution for data acquisition systems where accuracy, speed, cost and size are critical. Data and power are isolated from each other, so the circuit has excellent high-voltage tolerance while also effectively avoiding ground loop interference common in harsh industrial environments.

The circuit consists of an input signal conditioning stage, an ADC stage, and an output isolation stage. The ±10 V input signal is level shifted and attenuated by the U1A op amp, which is one half of the dual AD8606 . The output of this op amp is 0.1 V to 2.4 V, matching the input range of the ADC (0 V to 2.5 V), with a margin of 100 mV to maintain linearity. A buffered reference voltage (VREF =2.5 V) from the ADC is used to generate the required offset. The resistor values ​​can be modified to accommodate other common input ranges as described later in this circuit note.

The circuit design supports single power supply. The AD8606 is specified for a minimum output voltage of 50 mV (2.7 V supply) and 290 mV (5 V supply), a load current of 10 mA, and a temperature range of −40°C to +125°C. With a 3.3 V supply, load current less than 1 mA, and a narrower temperature range, a conservative estimate of the minimum output voltage is 45 mV to 60 mV.

Taking into account device tolerances, the minimum output voltage (lower end of range) is set to 100 mV to provide a safety margin. The upper limit of the output range is set to 2.4 V to provide 100 mV of headroom for positive swings at the ADC input. Therefore, the nominal output voltage range of the input op amp is 0.1 V to 2.4 V.

The other half of the AD8606 (U1B) is used to buffer the internal 2.5 V reference voltage of the AD7091R (U3) ADC.

The AD8606 was chosen for this application because of its low offset voltage (65 μV maximum), low bias current (1 pA maximum), and low noise (12 nV/√Hz maximum) characteristics. At 3.3V supply, power consumption is only 9.2 mW.

The output stage of the op amp is followed by a single-pole RC filter (R3/C9) to reduce out-of-band noise. The cutoff frequency of the RC filter is set to 664 kHz. An optional second-order filter (R4, C10 and R1, R2, C11) can be added to further reduce the filter cutoff frequency in the presence of low-frequency industrial noise. In such cases, the sampling rate of the AD7091R can be reduced due to the smaller signal bandwidth.

The AD7091R 12-bit 1 MSPS SAR ADC was chosen because of its ultra-low power consumption of only 349 A at 3.3 V (1.2 mW), which is significantly lower than any competing ADC currently on the market. The AD7091R also has a built-in 2.5 V reference with a typical drift of ±4.5 ppm/oC. The input bandwidth is 7.5 MHz, and the high-speed serial interface is SPI-compatible. The AD7091R is available in a small 10-pin MSOP package.

When powered from a 3.3 V supply, the total power dissipation of this circuit (excluding the ADuM5401 isolator) is approximately 10.4 mW.

Galvanic isolation is provided by the ADuM5401 quad-channel digital isolator (Grade C). In addition to isolating the output data, the ADuM5401 provides an isolated 3.3 V power supply for this circuit. The ADuM5401 is not required for normal operation of the circuit unless isolation is required. The ADuM5401 quad-channel 2.5 kV isolator integrates a DC/DC converter and is available in a small 16-pin SOIC package. The ADuM5401 consumes approximately 140mW at a 7 MHz clock frequency.

The AD7091R requires a 50 MHz serial clock (SCLK) to achieve a 1 MSPS sampling rate. However, the ADuM5401 (Grade C) isolator has a maximum data rate of 25 Mbps, which corresponds to a maximum serial clock frequency of 12.5 MHz. In addition, the SPI port requires that the trailing edge of SCLK drives the output data to the processor, so the total bidirectional propagation delay of the ADuM5401 (120 ns maximum) limits the upper clock limit to 1/120 ns = 8.3 MHz.

Although the AD7091R is a 12-bit ADC, the serial data is also formatted as 16-bit words to be compatible with the processor serial port requirements. Therefore, the sampling period TS includes the conversion time of the AD7091R650 ns plus 58 ns (additional time required by the data sheet, t1 delay + tQUIET delay), plus 16 clock cycles for the SPI interface data transfer.

T _S = 650 ns + 58 ns + 16 × 120 ns = 2628 ns
f _S = 1/T _S = 1/2628 ns = 380 kSPS

To provide a safety margin, it is recommended to set the SCLK and sample rate to a maximum value of 7 MHz and 300 kSPS respectively. The digital SPI interface can be connected to the microprocessor evaluation board using a 12-pin Pmod compatible connector (Digilent Pmod specification).

circuit design

 

 

The pre-calibration error is obtained by comparing the ideal transfer function calculated using the nominal values ​​of the components with the uncalibrated actual circuit transfer function. The tolerance of the resistors used in the actual measured circuit is ±1%. Test results do not include temperature changes.

Figure 3 shows the percent error (FSR) test results before and after calibration at ambient temperature. As shown in the figure, the maximum error before calibration is approximately 0.23% FSR. After calibration, the error is reduced to ±0.03% FSR, which is roughly equivalent to the 1 LSB error of the ADC.