This circuit is a flexible frequency-agile direct conversion IF to baseband receiver with a fixed 5 dB conversion gain that reduces cascade noise figure. Variable baseband gain is used to adjust signal level. The baseband ADC driver also includes a programmable low-pass filter to eliminate out-of-channel blocking and noise.

The bandwidth of this filter can be dynamically adjusted as the input signal bandwidth changes. This ensures that the available dynamic range of the ADC driven by this circuit is fully used.

The core part of this circuit is an integrated IQ demodulator, consisting of a fractional-N frequency-division PLL and a VCO. With only one (variable) reference frequency, the PLL/VCO can provide a local oscillator (LO) signal ranging from 750 MHz to 1150 MHz. Precise quadrature balance and low output DC offset ensure minimal impact on error vector magnitude (EVM).

The interfaces between all components in this circuit are fully differential. If DC coupling is required between different stages, the bias levels of adjacent stages should be compatible with each other.

Receiver architecture

The direct conversion (also called homodyne or zero-IF) architecture of the receiver is described in this circuit note. In contrast to a superheterodyne receiver, which can perform multiple frequency conversions, a direct conversion radio can perform only one frequency conversion. The advantages of primary frequency conversion are as follows:

• Reduce receiver complexity and reduce the number of stages required; improve performance and reduce power consumption
• Avoids image rejection issues and unwanted mixing products; only requires one LPF at baseband
• High sensitivity (adjacent channel rejection ratio [ACRR])

Figure 1 shows the basic schematic of the system, which consists of an integrated quadrature demodulator consisting of a fractional-N PLL and a VCO, followed by a programmable low-pass filter with variable baseband gain. The final part of the signal chain is an anti-aliasing filter and a dual-channel ADC.

Ideally, the input of the first stage and the output of the last stage should set the dynamic range (signal-to-noise ratio) of the system. In reality, this may not be the case.

IQ demodulator, fractional-N PLL and VCO

The input signal is applied to the ADRF6801 quadrature demodulator, which converts the frequency to zero IF. ADRF6801 integrates an on-chip frequency synthesizer to provide the required LO signal. The frequency synthesizer consists of a fractional-N PLL and VCO, providing an LO frequency range of 750 MHz to 1150 MHz in standard closed-loop mode.

The ADRF6801 uses two double-balanced mixers, one for the I channel and one for the Q channel. The LO provided to the mixer is generated using a divide-by-2 quadrature phase splitter. This provides the 0° and 90° signals for the I and Q channels respectively. The ADRF6801 provides approximately 5 dB of conversion gain from the RF input to the baseband I and Q outputs.

Low-pass filter, baseband variable gain amplifier (VGA) and ADC driver

Low-pass filter, baseband variable gain amplifier (VGA) and ADC driver low-pass filter, baseband gain and ADC driver functions are all implemented using the ADRF6510 . The signal applied to the ADRF6510 now has independent I and Q paths. The signal is first amplified through a preamplifier, then low-pass filtered to suppress any unwanted out-of-band signals and/or noise, and finally amplified through the VGA.

Each channel of ADRF6510 can be divided into three stages

• Preamplifier
• Programmable low pass filter
• VGA and output drivers

The preamplifier has user-selectable gain of 6 dB or 12 dB via the GNSW pin. The low-pass filter is programmable through the SPI port to a corner frequency of 1 MHz to 30 MHz in 1 MHz steps. The VGA has a 50 dB gain range and a gain slope of 30 mV/dB. The VGA gain is controlled through the GAIN pin, which ranges from −5 dB to +45 dB when the GNSW pin is pulled low, and from +1 dB to +51 dB when the GNSW pin is pulled high. The output drivers are capable of driving 1.5 V pp differential voltage into a 1 kΩ load while maintaining above 60 dBc for HD2 and HD3.

The maximum continuous wave (CW) signal that can be applied to the low-pass filter while still maintaining acceptable HD levels within the ADRF6510 is 2 V pp, where the gain is minimum (GNSW = 0 V, GAIN = 0 V).

The IQ signal from the ADRF6510 can be applied to an analog-to-digital converter (ADC) such as the AD9248, but passive low-pass filtering must first be deployed between the two stages.

Anti-aliasing filter

Passing the I and Q signals through anti-aliasing filters helps:

• Reduce out-of-band noise
• Reduce the output noise of the ADRF6510 (especially at higher gains)
• Reduce charge kickback from ADC
• Helps reduce out-of-band blockers (although they should be mitigated by the filtering capabilities of the ADRF6510)

The anti-aliasing filter is a low-pass filter designed to have a corner frequency range of approximately 30 MHz to 120 MHz. If the spectral content of the signal is known to be below 30 MHz, then a lower corner frequency can be selected.

A total of 5 anti-aliasing filters were tested in the system. The anti-aliasing filters tested in the first three tests were differential RC types, as shown in Figure 2. Filter 1 has R = 33, C = 18 pF. This results in a low-pass corner frequency of approximately 134 MHz.

Filter 2 has R = 33 Ω and C = 39 pF, so the low-pass corner frequency is 62 MHz. Finally, filter 3 has R = 33 Ω and C = 68 pF, so the corner frequency is 35.5 MHz. Filter 4 in Figure 3 is an LC filter with a corner frequency of 33 MHz; Filter 5 in Figure 4 is an RLC filter with a corner frequency of 33 MHz.

ADC

The signal from the anti-aliasing filter is applied to the ADC. The AD9248 is a dual-channel, 14-bit, 65 MSPS 3 V ADC that integrates a high-performance sample-and-hold amplifier and voltage reference.

Measurement results: EVM4 QAM of ADRF6510 and ADRF6510/ADRF6801 combination

A 5 MSPS modulated signal is applied to the input of the ADRF6801 quadrature demodulator, and the error vector magnitude (EVM) is measured. Use two AD8130-EBZ evaluation boards to convert the differential output signals of the ADRF6801 and ADRF6510 to single-ended signals. For more information on test setup, see the "Circuit Evaluation and Testing" section.

EVM is a measure of the performance quality of a digital transmitter or receiver, reflecting the deviation of actual constellation points from their ideal positions caused by amplitude and phase errors, as shown in Figure 5.

Figure 6 shows EVM versus ADRF6801 input power using only the ADRF6801 and the ADRF6801 followed by the ADRF6510. For the ADRF6801 and ADRF6510 curves, the sweep is the ADRF6510 gain change required to maintain a 1.5 V pp output voltage as the ADRF6801 input power. The preamplifier gain applied to the ADRF6510 is set to 6 dB.

When testing the ADRF6801 alone, note that for high input signal levels, EVM does not decrease until approximately +5 dBm input power is reached. But when the ADRF6801 drives the ADRF6510, the EVM will start to decrease at about 0 dBm input power. This is because the low-pass filter on the ADRF6510 can only handle 2 V pp when the preamp gain is set to 6 dB and the analog gain is at minimum, which is 1 V pp at the ADRF6510 input pin. Exceeding this signal level will cause distortion, causing EVM to drop.

For low input signal levels, the SNR becomes even lower and the EVM measurements start to degrade. When testing the ADRF6801 alone, EVM will begin to decrease at approximately −25 dBm. However, when the ADRF6801 drives the ADRF6510, EVM does not begin to decrease until −40 dBm. There is a decrease in EVM when measuring both devices at lower signal levels, primarily caused by noise generated by the ADRF6510. However, the noise floor of the bathtub plot is flatter and more consistent, and because of the baseband variable gain, the ability to resolve smaller signals is much better than when the ADRF6801 drives the ADRF6510.

For more detailed EVM measurements of the ADRF6510 and ADRF6801, please refer to their respective data sheets.

Measurement results: Complete signal chain including ADC

The signal chain in Figures 7 through 16 includes the ADRF6801, ADRF6510, and AD9248 . All three devices are DC coupled to each other. The common-mode voltage between the ADRF6801 and ADRF6510 is 2.6 V. The common-mode voltage between the ADRF6510 and AD9248 is 2.0 V. The ADC full-scale voltage is 2 V. The input power of the ADRF6801 is swept while changing the gain of the ADRF6510 to set the ADC input to the appropriate signal level of −3 dBFS. Measure SNR, SFDR, THD, HD2 and HD3 using ADC and Visual Analog software. Using an Agilent 8665B low phase noise signal generator, set the sampling rate to 65 MSPS. Two different ADRF6510 filter bandwidths are used: 5 MHz and 30 MHz. Additionally, the preamp gain of the ADRF6510 was changed from 6 dB to 12 dB. The RF signal input to the ADRF6801 is 895 MHz, and the LO signal is set to 900 MHz, resulting in a 5 MHz IF signal tone. Use 100 MHz as reference. The reference signal is divided by 4 to produce a 25 MHz PFD frequency. A Wenzel crystal oscillator model 119-3651-00 is used to generate a 100 MHz signal.

The data collected for this circuit note shows that the SNR (71.6 dB) and SFDR (80.5 dBc) performance of the AD9248ADC exceeds the performance of the ADRF6801 and ADRF6510 combination. The overall SNR and SFDR of the system are primarily limited by the output noise of the ADRF6510, which is rated at −130 dBV/√Hz at a gain of 20 dB and a filter bandwidth of 30 MHz, measured in the mid-band. (For more information on ADRF6510 noise versus gain and bandwidth settings, refer to the ADRF6510 data sheet).

The ADRF6510 filter exhibits compression characteristics (low gain in this case) at high input power levels, increasing harmonic distortion. Basically, at low input power levels, the ADC measures the output noise floor of the ADRF6510, and the HD2 and HD3 signal tones are below this noise floor. The ADRF6510 has an increased output noise floor due to its higher gain at lower input power.

Figures 7 and 8 show the SNR of the entire signal chain, including the ADC. At low power levels, the SNR drops almost dB by dB. The ADRF6510 has maximum gain and cannot continue to provide −3 dBFS at lower input power levels. The signal amplitude decreases while the noise remains relatively constant; therefore, the SNR decreases. The SNR reaches a constant level when the signal and gain are sufficient to reach −3 dBFS. The best SNR is obtained using anti-aliasing filter 3, although the spread is only about 1 dB across all filters except anti-aliasing filter 1, which makes the SNR worse compared to the rest.

When the ADRF6510 filter is set to 30 MHz, the SNR drops significantly at the highest input power, as shown in Figure 8. This is because the compression of the ADRF6510 filter causes a sudden drop in HD2 and HD3, while the overall noise floor increases dramatically.

Figures 9 and 10 show the SFDR of the entire system when using different anti-aliasing filters. Filter 4 and Filter 5 perform very poorly, with an SFDR of 40 dB over most of the input power range. This is because HD3 tone limits SFDR. For other anti-aliasing filters, SFDR exceeds 60 dB over most ranges. Since the main signal tone is not −3 dBFS, the SFDR decreases slightly when the input power is low.

At higher input power levels, the SFDR is limited by the harmonics generated by the compression of the ADRF6510 filter.

Figure 11, Figure 12, Figure 13 and Figure 14 show HD2 and HD3 of the system. Anti-aliasing filters 4 and 5 again show poorer performance, with HD2 performance around −55 dBc and HD3 only −40 dBc. Filters 1, 2, and 3 perform much better, with HD2 and HD3 better than −70 dBc.

At the low end of the input power range, the HD2 and HD3 components are smaller than the noise floor, and what is actually recorded is noise. After the gain of the ADRF6510 is reduced low enough, the output noise decreases and exhibits an HD signal tone, allowing appropriate measurements.

At the high end of the input power range, HD2 and HD3 drop off significantly. This is caused by the compression of the ADRF6510 filter.

Anti-aliasing filter performance summary

5 anti-aliasing filters tested and shown. Compared with LC and RLC type filters, RC type filters have much better harmonic distortion performance. When using the ADRF6510 to drive the AD9248, it is recommended to use an RC filter with the lowest possible corner frequency so that all indicators of the application can reach optimal values.

common mode scan

It is possible to use common-mode voltages other than 2 V between the output of the ADRF6510 and the input of the AD9248 while maintaining good performance.

Figures 15 and 16 show all standard specifications for common mode scanning. The system has good performance with common-mode voltages ranging from 1.5 V to 3 V. The performance degradation at low common-mode voltages is primarily caused by the ADRF6510, while the performance degradation at high common-mode voltages is caused by the combination of the ADRF6510 and AD9248. For the ADRF6510/AD9248, best performance is obtained by setting the common-mode voltage to 2.25 V.