Circuit functions and advantages

The circuit in Figure 1 is a 16-bit, 300 kSPS successive approximation analog-to-digital converter (ADC) system with a driver amplifier optimized for input signals up to 4 kHz and a 300 kSPS sampling rate, 10.75 mW low-power system.

This approach is extremely useful for portable, battery-powered, multi-channel applications that require low power consumption. It also provides advantages for applications where the ADC is idle most of the time between conversion bursts.

Typically, a high-performance successive approximation ADC driver amplifier is selected to handle a wide range of input frequencies. However, when an application requires a lower sampling rate, significant power savings can be achieved because lowering the sampling rate results in a corresponding reduction in ADC power consumption.

To fully take advantage of the reduced power consumption achieved by reducing the ADC sampling rate, a low-bandwidth, low-power amplifier is required.

For example, for applications with a maximum input of approximately 100 kHz and   an ADA4841-1 16-bit successive approximation register (SAR) ADC (3.5 mW at 500 kSPS, 2.1 mW at 300 kSPS), the ad7988- 5 80 MHz op amp (dissipates 12 mW at 10 V). Total system power consumption, including   the ADR435 reference (4.65 mW at 7.5 V), is 18.75 mW at 300 kSPS.

For input bandwidths below 4 kHz and sample rates below 300 kSPS, the OP1177 1.3 MHz op amp (4 mW at 10 V) provides excellent signal-to-noise ratio (SNR) and total harmonic distortion (THD) performance and reduces total system power consumption from 18.75 mW to 10.75 mW at 300 kSPS, a reduction of 43%.

Circuit description

This circuit contains the AD7988-5 ADC, OP1177 amplifier, and ADR435 voltage reference. The AD7988-5 is a 16-bit, 500 kSPS SAR ADC with low power consumption that scales with the sample rate, consuming 3.5 mW at 500 kSPS. In addition to low power consumption, it offers industry-leading AC performance: SNR = 91 dB, THD = −114 dBc.

The driving amplifier uses OP1177, a low-power, precision device with a power supply current of 400 A and a gain bandwidth product of 1.3 MHz. The OP1177 can operate from supplies ranging from 5 V to 30 V. The ADC's reference voltage source is the ADR435, which is a high-precision, low-noise, 5 V XFET voltage reference source. At low supply current (620 A), the ADR435 has an extremely low temperature coefficient (3 ppm/°C). At 300 kSPS, the total power consumption of this circuit is 10.75 mW. Signal-to-noise ratio (SNR) is 90.6 dBFS, total harmonic distortion (THD) is −102 dBc, and input frequency is up to 4 kHz.

The OP1177 is configured as a unity gain buffer and has an RC filter (200 Ω, 2.7 nF) with a cutoff frequency of 295 kHz between it and the AD7988-5. The filter allows the use of a noisier amplifier such as the OP1177, which still has much lower power consumption at 8nV/√Hz. Higher noise is traded for lower power consumption at the expense of only a 0.4 dB degradation in system signal-to-noise ratio (SNR) performance. The higher R value (200 ) relative to the value recommended in the data sheet (20 ) means that the OP1177 can drive a large input capacitance of 2.7 nF. Higher R values ​​limit the maximum input bandwidth to a few kHz, resulting in lower distortion.

For inputs up to 5 kHz, the OP1177 achieves 16-bit distortion performance (THD below −100 dBc). Distortion increases above 5 kHz, so use of this circuit is not recommended at higher input frequencies, and use of this amplifier in multiplexer applications is not recommended due to the long settling time. Note that the OP1177 requires at least 1.5 V input headroom/footroom and 1 V output headroom/floor when setting the supply. It should also be noted that the OP1177 cannot be used to drive the AD7988-5 above 300 kSPS because the driver settling time is not sufficient for the shorter ADC acquisition time (see Figure 3).

Performance results

The purpose of this circuit is to provide good AC performance at the lowest possible ADC driver power consumption level at input frequencies below 4 kHz and a sampling rate of 300 kSPS. Figure 2 shows an FFT plot of circuit performance at 4 kHz input. The signal-to-noise ratio (SNR) is 90.6 dBFS and the total harmonic distortion (THD) is −102 dBc. The main reason for the slight decrease in the AD7988-5's signal-to-noise ratio (SNR) compared to the 91 dBFS specification is that the OP1177 has slightly higher noise at 8 nV/√Hz than the ADA4841-1's 2 nV/√Hz. Total system power consumption is 10.75 mW, including: 2.1 mW for the ADC (sampling rate 300 kSPS), 4 mW for the amplifier, and 4.65 mW for the reference. This represents a 43% reduction in power consumption compared to the 12 mW of the ADA4841-1, resulting in a total system power consumption of 18.75 mW.

Figure 3 shows how the total harmonic distortion (THD) of the system increases and the signal-to-noise ratio (SNR) decreases at higher sampling rates beyond 300 kSPS. For this reason, optimal performance is obtained by operating the ADC at 300 kSPS or less.

Figure 4 shows that as the input frequency exceeds 4 kHz, the system total harmonic distortion (THD) increases and the signal-to-noise ratio (SNR) decreases. This is due to amplifier distortion, which can be seen from the total harmonic distortion plus noise (THD+N) versus frequency plot in Figure 5.