Circuit description

A clock set to a user-programmable frequency modulates one of the three LED colors using a constant-current driver consisting of the AD8615 op amp , the ADG819 switch, and the AD5201 digital potentiometer . The spectroscope sends half of the light through the sample container and the other half through the reference container. The ADA4528-1 configured as a transimpedance amplifier then converts the photodiode current into an output voltage square wave whose amplitude is proportional to the light transmitted from the sample or reference container. The transimpedance amplifier utilizes the ADG633 single-pole double-throw (SPDT) switch to select one of two transimpedance gains. The AD7175-2 Σ-Δ ADC samples the voltage and sends the digital data to the FPGA for digital demodulation.

The FPGA first synchronizes a digitally generated sine wave with the LED clock and then multiplies this sine wave with the ADC sample data to achieve synchronous demodulation. Additionally, a 90° phase-shifted version of this sine wave is also multiplied with the ADC data to obtain the quadrature component of the modulated signal. The result of these operations is the generation of two low-frequency demodulated signals, representing the in-phase and quadrature components of the light received by each channel. A narrowband FIR low-pass filter filters out all other frequency components, making it easy to calculate the amplitude and phase shift of the signal measured by the photodiode, while light or electrical noise at frequencies different from the LED clock is suppressed. The ADG704 multiplexer connects the supply rail to one of three color LEDs, allowing the user to select the test wavelength via a 2-bit address. AD8615 and NPN transistor form a simple current source, and the LED current is given by the following formula:



where:
V _{NON-INVERTING} is the non-inverting input voltage of AD8615.
REMITTER _is the value of the resistor connected to the emitter of transistor Q3.

The ADG819 SPDT switch is connected to the setpoint voltage and ground, and its control pin is connected to the reference clock. As the clock oscillates between high and low, the current source's set point changes from 0 mA to the desired output current, producing a square wave signal.

The AD5201 digital potentiometer acts as a programmable resistor divider to the 2.5 V reference, allowing a total of 33 different current output settings for the LED current.

The sample and reference containers each receive half of the LED light energy, and the amount of light absorbed depends on the type and concentration of the medium in each container. A photodiode on the other side of each container generates a small amount of current, proportional to the amount of light received.

The first stage of each receiver channel contains the ADA4528-1 op amp, which is configured as a transimpedance amplifier to convert the photodiode output current to a voltage. The ADA4528-1 is an auto-zero amplifier that introduces negligible offset, no 1/f noise, and very low broadband noise (5.9 nV/√Hz). Like all autozero amplifiers, there is a noise spike at the autozero frequency. For the ADA4528-1, this frequency is approximately 200 kHz, but the circuit signal bandwidth rolls off long before that.

The op amp input bias current multiplied by the feedback resistor value at the output is the offset voltage. The op amp's input offset voltage appearing at the output will be amplified with a gain determined by the feedback resistor and the photodiode shunt resistor. Additionally, any input voltage offset of the op amp will appear across the photodiode, causing an increase in photodiode dark current. The ADA4528-1 has a very low offset voltage (2.5 μV), making it ideal for this application.

Figure 2 shows a typical transimpedance amplifier with a single feedback resistor and its ideal transfer function.

Figure 2. Transimpedance Amplifier Transfer Function

Because some of the solutions being tested can have very strong absorptive properties, it is sometimes necessary to use a large feedback resistor to measure the very small currents produced by the photodiode while also being able to measure the currents corresponding to highly dilute solutions. High Current. To solve this problem, the photodiode amplifier in Figure 1 contains two different selectable gains. One gain is set to 33 kΩ and the other is set to 1 MΩ. When a single SPDT switch is connected to the output of the op amp to switch the feedback resistor, the ADG633's on-resistance causes a transimpedance gain error. To avoid this problem, Figure 3 shows a better configuration in which the ADG633 inside the feedback loop selects the desired resistor, while a second switch connects the next stage of the system to the selected feedback loop. The voltage at the output of the amplifier is:



It represents the gain error. However, because one of the ADG633s is outside the feedback loop, the output impedance of this stage is the on-resistance of the ADG633 (typically 52 Ω), rather than the very low output impedance associated with the op amp output in closed-loop operation. The error caused by the ADG633 leakage current (5 pA typical) is negligible.

Even the best rail-to-rail output amplifiers, such as the ADA4528-1, cannot fully swing their output to the supply rail. Additionally, the input offset voltage on the ADA4528-1 can be negative, albeit very small. Rather than running through a negative supply to ensure that the amplifier never clips and that it can drive to 0.0 V, the op amp ADA4805-1 provides a 100 mV buffer voltage to bias the photodiode anode and the ADA4528-1. The ADA4805-1 is ideal for use as a reference buffer because it maintains unity gain stability when driving decoupled large capacitive loads. A second ADA4805-1 is also used to buffer the output of the AD5201 digital potentiometer that sets the LED current.

Figure 3. Programmable gain transimpedance amplifier.

The photodiode amplifier output voltage can swing from 0.1 V to 5.0 V. For the 33 kΩ range, the 4.9 V output range corresponds to a full-scale photodiode current of 148.5 μA. For the 1 MΩ range, this corresponds to a full-scale photodiode current of 4.9 μA. When operating with a gain setting of 1 MΩ, it is important to protect the photodiode from external light to prevent amplifier saturation. Although the synchronous detection scheme described below can effectively attenuate any frequency that is not synchronized with the LED clock, it will not work properly if the ADC returns saturated data.

Gain settings for each channel can be independently selected via the FPGA board.

ADC sampling rate and modulation frequency selection
AD7175-2 ADC is configured with a sinc5+sinc1 filter, the output data rate is 250 kSPS, and can sample two channels in a single cycle. This configuration results in an effective sampling rate of 25 kSPS for each channel (each channel outputs data every 40 μs). Any frequency above 12.5 kHz (such as the odd harmonics of the square wave modulation) will be aliased back into the ADC passband. The synchronous demodulation stage suppresses these frequencies as long as they are not just above the modulation frequency. In order to prevent the aliasing frequency of the modulation waveform from folding back to the fundamental frequency, the modulation frequency should be selected according to the following relationship:



where:
F _MODULATION is the modulation frequency.
F _SAMPLE is the ADC effective output data rate.

For example, in this system, the effective output data rate is 25 kSPS, so if a modulation frequency of around 1 kHz is required, this frequency must be 1020 Hz (n = 12) or 943 Hz (n = 13) to avoid aliasing issues. Sampling this method selects the modulation frequency, eliminating the need for steep anti-aliasing filters at the front end.

Digital synchronous detection
This circuit does not implement synchronous detection in hardware (see circuit note CN-0312 ), but obtains time sampling data and uses FPGA to implement digital synchronous detection. Figure 4 is a schematic diagram of the digital synchronous detection module implemented in FPGA. The FPGA generates an AC excitation signal to drive the LED, and a digitally generated sine wave locks the signal in a digital phase-locked loop. The input signal is multiplied with a digital sine wave and a 90° phase-shifted version, producing two low-frequency demodulated signals that are proportional to the in-phase and quadrature components of the input signal at the modulation frequency. As shown in Figure 4, the amplitude is the root of the sum of the squares of these two components. For more information about this demodulation technique, see the "Learn More" section.

Figure 4. System block diagram including FPGA synchronous detector.

Power supply The
EVAL-CN0363-PMDZ board is powered by an external 6 V to 12 V DC power supply. The analog portion of the circuit is powered by AVDD = 5 V from the low dropout regulator ADP7102 . The digital portion of the circuit is powered by IOVDD = 3.3 V generated by the low dropout regulator ADP1720 . Alternatively, IOVDD can be provided by the PMOD connector VCC via the link option.

The 2.5 V reference voltage is provided by the AD7175-2 ADC's internal 2.5 V reference source.

Circuit Performance Measurements
To verify the noise performance of the system, data should be acquired with all LEDs disabled. The synchronous detector still operates at the LED clock frequency, but will not detect any light signals synchronized with this clock, therefore, it will cancel all DC and AC signals.

Table 1 shows the noise-free bit performance.

Table 1. Noise-free bit ^performance1

^1Sampling rate = 25 kSPS, excitation frequency = 1020 Hz, output filter bandwidth = 100 Hz.