The circuit shown in Figure 1 uses the AD5700 , the industry's lowest power and smallest HART® 1-compatible IC modem, and the AD5422 16-bit current and voltage output DAC to form a complete HART-compatible 4 mA to 20 mA solution. The use of the OP184 in this circuit allows the I _OUT and V _OUT pins to be shorted together, thereby reducing the number of screw connections required in programmable logic control (PLC) module applications. To further save space, the AD5700-1 provides an internal oscillator with 0.5% accuracy.

Application note AN-1065 describes how to configure the AD5420 I _{OUT DAC to comply with the HART communication standard.} AN-1065 outlines how the AD5700HART modem output is attenuated and ac coupled to the AD5420 through the CAP2 pin. The same is true for the AD5422. However, if the application involves a particularly harsh environment, an alternative circuit configuration with better power supply rejection characteristics may be used. This alternative circuit requires the use of an external R _SET resistor and involves coupling the HART signal to the R _SET pin of the AD5420 or AD5422 . CN-0270 describes this solution with the AD5420, typically in line-powered transmitter applications. The current circuit note relates to the AD5422; unlike the AD5420, this device provides both voltage and current output pins, making it particularly suitable for PLC/distributed control system (DCS) applications. The AD5422 is available in 40-pin LFCS and 24-pin TSSOP packages. The relevance of this to the circuit characteristics will be introduced in the "Circuit Description" section.

The circuit complies with the HART physical layer specifications defined by the HART Communication Foundation, such as output noise during silence and analog slew rate specifications.

For many years, 4 mA to 20 mA communications have been used in process control instrumentation. This communication method is stable and reliable, and has high immunity to environmental interference in long-distance communications. However, the limitation is that only one process variable can be communicated in one direction at a time.

The Highway Addressable Remote Transducers (HART) standard was developed to enable high-performance bidirectional digital communications while supporting the 4 mA to 20 mA analog signals used by traditional instrumentation equipment. It derives various features such as remote calibration, troubleshooting and transmission of additional process variables. Simply put, HART is a digital two-way communication that modulates a 1 mA peak-to-peak Frequency Shift Keying (FSK) signal on top of a 4 mA to 20 mA analog current signal.

Figure 1 shows how the AD5422 can be used with the AD5700 HART modem and UART interface to enable HART support for the 4 mA to 20 mA current outputs commonly used in PLC and DCS systems. If the application does not require shorting the I _OUT and V _OUT pins, a buffer connected to the +V _SENSE pin is not necessarily required. The HART_OUT signal from the AD5700 is attenuated and AC coupled to the RSET pin of the AD5422. If the external R _SET resistor is not used, an alternative method of connecting the AD5422 and AD5700 through the CAP2 pin is provided in application note AN-1065, as discussed previously. This method only works with the 40-pin LFCSP package option of the AD5422 because the lower pin count 24-pin TSSOP package does not have a CAP2 pin.

Determine external component values

Capacitors C1 and C2 can be used with the device's digital slew rate control feature to control the AD5422 's I _OUT signal slew rate. When determining the absolute value of the capacitor, ensure that the modem's FSK output passes without distortion. Therefore, the bandwidth of the modem output signal must pass the 1200 Hz and 2200 Hz frequencies. Figure 3 shows the circuit that implements this requirement. In this case, C2 (shown in Figure 1) remains open.

The low-pass and high-pass filter circuits are formed through the interaction of R _H , _CL , _CH and C ₁ in conjunction with some internal circuitry of the AD5422. When calculating the values ​​for these components, target low-pass and high-pass frequency cutoff points of >10 kHz and <500 Hz, respectively. Figure 4 shows a plot of the simulated frequency response, and Table 1 shows the effect on the frequency response of adding components while keeping the remaining component values ​​constant.

The output of the modem is an FSK signal including 1200 Hz and 2200 Hz frequency shifts. This signal must be converted to a 1 mA peak-to-peak current signal. To do this, the signal amplitude on the R _SET pin must be attenuated. This is because the AD5422 is designed with an internal current gain configuration. Assuming that the modem's output amplitude is 500 mVp-p, its output must be attenuated by a factor of 500/150 = 3.33. This attenuation is achieved through R _H and _CL .

The measurements in this circuit note were made using the following component values:

• C1 = 4.7 nF
• R _H = 27 kΩ
• C _L = 4.7 nF
• C _H = 8.2 nF

Figure 5 shows that frequency shifts of 1200 Hz and 2200 Hz were measured on a 500Ω load resistor. Channel 1 shows the modulated HART signal coupled to the AD5422 output (set to output 4 mA), and Channel 2 shows the AD5700 TXD signal.

HART compatibility

To be compatible with HART, the circuit in Figure 1 must comply with the HART specification. The HART specification document contains many physical layer specifications. The two important ones are output noise during silence and analog slew rate.

Output noise during silence

Noise should not be coupled onto the network in the HART extended band when the HART device is not transmitting (quiet). Excessive noise may interfere with the device itself or other devices on the network receiving HART signals.

Voltage noise measured on a 500Ω load must contain no more than 2.2 mV rms of broadband noise and associated noise in the extended frequency band. This noise is measured by connecting an HCF_TOOL-31 filter (available from the HART Communications Foundation) across a 500Ω load and connecting the filter output to a true rms meter (see Figure 6). You can also use an oscilloscope to check the peak-to-peak voltage of the output waveform.

AD5422 output current settings are 4 mA, 12 mA, and 20mA. The results with the bandpass filter are very similar for all three output current values, although the wide bandwidth noise increases slightly as the current output value increases. At an output current of 4 mA, the measured rms values ​​were 143 μV rms and 1.4 μV rms with and without the HCF_TOOL-31 bandpass filter, respectively. Both values ​​are within the required 2.2 mV rms (with HART filter) and 138 mVrms (wideband noise without HART filter) specifications. At an output current of 12 mA, the measured rms values ​​are 158 μV rms and 2.1 μV rms with and without the HCF_TOOL-31 bandpass filter, respectively, both of which are also within the HART protocol specification. In the range.

Figure 7 and Figure 8 show oscilloscope plots of 4 mA and 12 mA output current, respectively. Note that the filter has a passband gain of 10. Channel 1 and Channel 2 on each graph show the input and output of the filter respectively.

simulated rate of change

This specification ensures that the maximum rate of change of analog current does not interfere with HART communications when the device regulates current. Step changes in current can disrupt the HART signal. Still use the same test circuit shown in Figure 6. For this test, the AD5422 was programmed to output a periodic waveform switching from 4 mA to 20 mA with no delay at either value for maximum rate of change. To comply with HART specifications, the peak voltage of the waveform at the filter output cannot be greater than 150 mV. Compliance with this requirement ensures that the maximum bandwidth of the analog signal is within the specified DC to 25 Hz frequency band.

The normal time for the AD5422 output to change from 4 mA to 20 mA is about 10 μs. This speed is obviously too fast and will cause significant damage to the HART network. In order to reduce the change rate, the AD5422 provides two features: one is to connect capacitors at the CAP1 and CAP2 pins, and the other is to provide an internal linear digital slew rate control function (please refer to the AD5422 data sheet for details ). For faster slew rates, a nonlinear digital ramp generator can be implemented on the controller/FPGA communicating with the AD5422.

To reduce the bandwidth below 25 Hz, very large capacitor values ​​are required at the CAP1 and CAP2 pins. The best solution is to use an external capacitor in conjunction with the AD5422 's digital slew rate control feature. The purpose of the two capacitors, C1 and C2, is to reduce the rate of change of the analog signal; however, this is not sufficient to meet the specification. Enabling the slew rate control feature provides flexibility in setting the slew rate.

Figure 9 shows the output of the AD5422 and the output of the HART filter. The peak voltage at the filter output is 82 mV, which is within the specified range. The slew rate is set to SR clock = 3 and SR step = 2, the transition time from 4 mA to 20 mA is set to approximately 120 ms, C1 = 4.7 nF, C2 is not connected. If this rate of change is too low, the slew time can be shortened. Using the circuit configuration with C1 = 4.7 nF and C2 unconnected, it can be seen that when the slew time is set to 80 ms (SR clock = 1, SR step = 2), the resulting simulated slew rate complies with the HART specification. However, further shortening the slew time to 60 ms (SR clock = 0, SR step = 2) results in results outside the 150 mV specification. A capacitor connected from CAP1 to AVDD can be used to offset the increase in peak voltage at the filter output caused by a fast slew time. However, care must be taken when selecting this value because it affects the low-pass filter cutoff frequency discussed in the "Determining External Component Values" section.

Figure 10 shows the results of changing the slew rate control setting to SR clock = 5, SR step = 2 and keeping the C1 capacitor value unchanged at 4.7 nF. In this way, the conversion time will be around 240 ms. The peak amplitude at the filter output can be further reduced by increasing the C1 value, configuring a slower slew rate, or a combination of both.

Transient voltage protection

The AD5422 has built-in ESD protection diodes to prevent damage caused by normal operation. However, industrial control environments subject I/O circuits to much higher transients. To prevent excessive transient voltages from affecting the AD5422 , external power diodes and inrush current limiting resistors may be required, as shown in Figure 1. The constraint on the resistor value (shown as 18Ω in Figure 1) is that during normal operation, the output level of I _{OUT must remain within its compliance voltage limit (AV DD} − 2.5 V), and the two protection diodes and the resistor must have the appropriate power rating. At 18Ω, the compliance limit at the pin is reduced by V = I _MAX × R = 0.36 V for a 4 mA to 20 mA output. A 10 kΩ resistor is also connected to the positive input of the OP184 buffer to limit the current during transients to protect the amplifier. Further protection can be achieved through transient voltage suppressors (TVS) or transient absorbers. These components include unidirectional and bidirectional suppressors, available in a wide variety of isolation and breakdown voltage ratings. TVS should be calibrated with the lowest breakdown voltage as much as possible, and at the same time, it should not conduct within the functional range of the current output. It is recommended to secure all remotely connected nodes.

In many process control applications, it is necessary to provide an isolation barrier between the controller and the controlled unit to protect and isolate the control circuitry and prevent dangerous common-mode voltages from damaging the circuitry.

Analog Devices' iCoupler family of products isolates voltages above 2.5 kV. For more information about iCoupler products, please visit www.analog.com/icouplers To reduce the number of isolators required, non-critical signals such as CLEAR can be connected to GND; FAULT and SDO can be left unconnected, thus only three signals need to be isolated. Note, however, that the FAULT or SDO pin is required to access the fault detection functionality of the AD5422 .