Low-Voltage Differential Signaling (LVDS) is an established standard for low-power, high-speed, point-to-point communications (TIA/EIA-644). It is used in instrumentation and control applications to transmit large amounts of data over a backplane or short cable links, or to distribute high-speed clocks to different parts of the application circuit.

The circuit shown in Figure 1 represents the isolation of an LVDS interface. The benefits of isolating an LVDS interface include protecting the device from faults (safety isolation) and increasing robustness (functional isolation).

The ADuM3442 provides digital isolation for the logic inputs of the ADN4663 LVDS driver and the logic outputs of the ADN4664 LVDS driver. In addition to using the ADuM5000 to provide isolated power, there are many challenges associated with isolating LVDS links in industrial and instrumentation applications, including:

• The logic signals are isolated from the LVDS driver/receiver, ensuring standard LVDS communication on the bus side of the circuit.
• The highly integrated isolation uses only two additional wide-body SOIC devices (ADuM3442 and ADuM5000) to isolate standard LVDS devices (ADN4663 and ADN4664).
• Lower power consumption compared to traditional isolation (optocoupler). One of the characteristics of LVDS applications is low power operation.
• Multi-channel isolation. In LVDS applications, parallel channels are used to maximize data throughput. This circuit demonstrates 4-channel isolation (two transmit channels and two receive channels in this example).
• High working speed; the maximum working speed reaches 150 Mbps, easily meeting the speed requirements of basic LVDS.

The circuit shown in Figure 1 isolates a dual-channel LVDS line driver and a dual-channel LVDS receiver. It enables two complete transmit and receive paths on a single circuit board.

Applications for isolated LVDS include safety isolation and/or functional isolation of inter-board, backplane and printed circuit board (PCB) communication links. Safety isolation can be used, for example, when one or more plug-in cards in an LVDS backplane system are at risk from high voltage transients. Isolating the LVDS interface ensures that such fault conditions do not affect other circuits in the system. Functional isolation is useful in some situations, such as measuring equipment. Isolating the LVDS link between the ADC and FPGA provides a floating ground plane, improving measurement data integrity and reducing interference from other parts of the application.

Figure 2 shows an isolated LVDS interface circuit that isolates two transmit communication channels (CMOS/TTL to LVDS) and two receive channels (LVDS to CMOS/TTL). The isolated signal is capable of data rates up to 150Mbps while maintaining  the ADuM3442 's maximum pulse width distortion specification.

Logic levels can be applied to IN1 and IN2 and are isolated by the ADuM3442. The corresponding outputs of the ADuM3442 (DIN1 and DIN2 test pins) are connected to the ADN4663 LVDS driver to establish LVDS signals on DOUT1+, DOUT1− and DOUT2+, DOUT2−.

The ADN4664  LVDS receiver can receive LVDS signals on RIN1+, RIN1− and RIN2+, RIN2−. The receiver outputs (ROUT1, ROUT2 test pins) are connected to the ADuM3442 for signal isolation. The corresponding logic outputs of ADuM3442 are OUT1 and OUT2.

The circuit is powered from the logic side by connecting VDD1. The power supply can be 3.3 V or 5 V, powering the logic side of the ADuM3442 (circuit signal isolation) or powering the ADuM5000, which provides isolated power to the bus side of the circuit.

The ADuM5000's output V _ISO provides 3.3 V power to the LVDS driver (ADN4663) and LVDS receiver (ADN4664), as well as the bus side of the ADuM3442.

The circuit layout was performed as described in the AN-0971 application note "Recommendations for Radiation Control of IsoPower Devices" guide. Additionally, the layout is optimized for high-speed differential signaling. LVDS input/output trace lengths are matched and have an impedance of 50Ω to ground (100Ω between differential pairs). Each pair of test points is equally distanced from the driver/receiver. Multiple ground vias line the traces to increase signal integrity during high-speed operation.

The LVDS inputs RIN1+, RIN1− and RIN2+, RIN2− are connected to 100Ω terminal resistors (R1, R2). Terminate any bus sink connected to DOUT1+, DOUT1− and DOUT2+, DOUT1−.

Power and ground are connected to each other via spiral cable connectors (VDD1 and GND1). Logic inputs (IN1, IN2)/outputs (OUT1, OUT2) are connected to each other via 4 SMB connectors. Bus signals are connected in a similar manner via 8 SMB connectors. They are connected via traces to the LVDS driver (ADN4663) and receiver (ADN4664) with an impedance of 50Ω to ground.