The circuit shown in Figure 1 is a 75 MHz wideband receiver front end based on the ADL5202 wide dynamic range, high speed, digitally controlled variable gain amplifier (VGA) and the 14-bit, 250 MSPS AD9643 digital converter (ADC).

The fifth-order Butterworth anti-aliasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss caused by the filter network and other resistive components is approximately 2.3dB. The overall circuit (integrated bandpass filter) has a 1dB bandwidth of 75 MHz (145 MHz to 220 MHz) and a 3dB bandwidth of 110 MHz (120 MHz to 230 MHz). Passband flatness is 1 dB.

This circuit is optimized for processing 75 MHz bandwidth IF signals centered at 182.5 MHz (second Nyquist frequency region) and sampled at 245.76 MSPS. Using a 182.5 MHz analog input in the 75 MHz band, the measured signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) were 68.4 dBFS and 80.7 dBc, respectively.

The circuit shown in Figure 1 accepts a single-ended input and converts it to a differential input signal using a wide-bandwidth (5 MHz to 300 MHz) M/A-COM TC3-1T+ 1:3 (Z) transformer. The ADL5202 6.0 GHz differential amplifier has a 150Ω differential input impedance and supports three different gain settings: 0 dB, 10 dB, and 20 dB.

The ADL5202 is an ideal driver for the AD9643 , which enables a fully differential architecture in the ADC via bandpass filters, providing good high-frequency common-mode rejection while minimizing second-order distortion products. The ADL5202 has a programmable gain range from −11.5 dB to 20 dB in 0.5 dB steps. Three gain settings are used in this circuit to illustrate the high performance of the ADL5202 and AD9643.

The filter network has an insertion loss of approximately 2.3 dB; the amplifier gain can be used to compensate for this loss when programming the ADL5202 to provide positive gain values ​​above 2.3 dB. Gain also helps minimize the noise effects of the amplifier. .

The antialiasing filter is a fifth-order Butterworth bandpass filter designed using a standard filter design program (in this case, the Advanced Design System [ADS] from Agilent). The Butterworth filter was chosen because of its flat response. Other filter design programs are available from Nuhertz Technologies or QuiteUniversal Circuit Simulator (Qucs) Simulation.

For best performance, the ADL5202 should be loaded with a net differential load of 150Ω. The 1μH inductor biases the output stage of the ADL5202, and the series capacitor isolates the filter and ADC from this bias voltage at the amplifier output. The output of the ADL5202 has an impedance load of about 145Ω. This impedance comes from the termination resistors at the filter input and output, as well as the ADC resistor and the series damping resistor at the ADC input.

A 20Ω resistor in series with the ADC input isolates internal switching transients from the filter and amplifier. Two 162Ω resistors are placed in parallel with the ADC to lower the input impedance of the ADC, making performance more predictable.

The differential input impedance of the AD9643 is approximately 3 kΩ in parallel with 2.2 pF. For this type of switched-capacitor input ADC, the real and imaginary parts are a function of the input frequency; see application note AN-742 for detailed analysis .

The fifth-order Butterworth filter is designed with a source impedance of 100Ω, a load impedance of 293Ω, a 1dB bandwidth of 75MHz, and a 3dB bandwidth of 110MHz. The final circuit values ​​of the filter are shown in Figure 2. The values ​​chosen for the filter passive components are the closest standard values ​​to the program-generated values. The ADC's internal 2.2pF capacitor is used as part of the final shunt capacitor in the filter design. This shunt capacitance at the ADC input helps reduce kickback charge current in the ADC input sampling network and optimizes filter performance.

Table 1 summarizes the measured performance of the system with a 3 dB bandwidth of 110 MHz. The total insertion loss of the network is approximately 2.3 dB.

Figure 3 shows the bandwidth response of the final filter circuit, and Figures 4 and 5 show the SNR and SFDR performance.

Filter and interface design program

This section introduces common methods for amplifier/ADC and filter interface design. To achieve optimal performance (bandwidth, SNR, and SFDR), amplifiers and ADCs should impose certain design constraints on general circuits, such as:

• The amplifier must refer to the correct DC loading recommended by the data sheet for optimal performance.
• A DC bias inductor must be used between the amplifier and the power supply to properly bias the amplifier output.
• The input impedance of the ADC must be reduced by an external parallel resistor, and the correct series resistor must be used to isolate the ADC from the filter. This series resistor will also reduce signal spikes.

This design approach tends to take advantage of the relatively high input impedance of most high-speed ADCs and the relatively low impedance of the driving source to minimize the insertion loss of the filter.

For details on the design procedure, see circuit notes CN-0227 , CN-0238 , and CN-0279 .

Circuit Optimization Techniques and Tradeoffs

The parameters within this interface circuit are highly interactive; therefore optimizing all critical specifications of the circuit (bandwidth, bandwidth flatness, SNR, SFDR, and gain) is nearly impossible. However, by changing the driver amplifier output series resistor (for low impedance output) and/or the resistor in series with the ADC input (20Ω in the circuit shown in Figure 1), it is possible to minimize the distortion that typically occurs within the bandwidth response. Signal spikes.

The series resistor at the ADC input is chosen to minimize distortion caused by any residual charge injection (from the ADC's internal sampling capacitance). Increasing this resistance also tends to reduce signal spikes within the band.

However, increasing the ADC input series resistance also increases signal attenuation, so the amplifier must drive a larger signal to fill the ADC's input range.

Another way to optimize passband flatness is to slightly change the filter shunt capacitance.

The ADC input termination resistor (364Ω in the circuit shown in Figure 1) should generally be selected so that the net ADC input impedance is between 200Ω and 400Ω. Keeping the resistor within this range reduces the effect of the ADC input capacitance and may stabilize the filter design; however, this increases the circuit's insertion loss. Increasing this value will also reduce signal spikes.

The trade-offs between the above factors can be somewhat difficult. In this design, each parameter is equally weighted; therefore, the values ​​selected represent the interface performance for all design features. In some designs, different values ​​may be chosen to optimize SFDR, SNR, or input drive levels, depending on system requirements.

The SFDR performance of this design depends on two factors: amplifier and ADC interface component values, as shown in Figure 1. The final SFDR performance numbers shown in Table 1 and Figure 4 are obtained after optimizing the filter design, taking into account the board parasitic capacitance and non-ideal components used in the filter design.

Another factor that can be weighed in this particular design is the ADC full-scale range setting. For the data obtained with this design, the full-scale ADC differential input voltage was set to 1.75 V pp, which optimizes SFDR. Changing the full-scale input range to 2.0 V pp slightly improves SNR, but the SFDR performance is slightly degraded. Changing the full-scale input range in the opposite direction to 1.5 V pp slightly improves SFDR, but SNR performance is slightly degraded.

The signal in this design is ac-coupled with a 0.1µF capacitor to block the common-mode voltage between the amplifier, its termination resistor, and the ADC input. For more details on common-mode voltage, see the AD9643 data sheet.

Passive Components and PCB Parasitics Considerations

The performance of this or any high-speed circuit is highly dependent on proper printed circuit board (PCB) layout, including but not limited to power supply bypassing, controlled impedance traces (if required), component placement, signal routing, and power and ground planes . For more details on high-speed ADC and amplifier PCB layout, see guides MT-031 and MT-101 .

For passive components within the filter, use low parasitic surface mount capacitors, inductors, and resistors. The selected inductor is from the Coilcra0603CS series. The surface mount capacitor used in the filter is 5%, C0G, 0402 type to ensure stability and accuracy.

For complete documentation of the system, including schematics, bill of materials, and PCB layout, see the CN-0242 Design Support Package .