The circuit shown in Figure 1 converts a high-frequency single-ended input signal to a balanced differential signal for driving the AD7626 16-bit 10 MSPS PulSAR® ADC . This circuit uses a low-power differential amplifier ADA4932-1 to drive the ADC to maximize the high-frequency input signal tone performance of the AD7626. The real advantage of this device combination is low power consumption and high performance.

The AD7626 has dynamic performance that breaks industry standards, with a signal-to-noise ratio of 91.5 dB at 10 MSPS, 16-bit INL performance, no latency, LVDS interface, and power consumption of only 136 mW. The AD7626 uses a SAR architecture. Its main feature is that it can sample at 10 MSPS without delay, without the "pipeline delay" that often occurs in pipelined ADCs, and at the same time has excellent linearity.

The ADA4932-1 features low distortion (100 dB SFDR at 10 MHz), fast settling time (9 ns to 0.1%), high bandwidth (560 MHz, -3 dB, G = 1), and low current (9.6 mA). Ideal for driving the AD7626. It also easily sets the desired output common-mode voltage.

This combination provides industry-leading dynamic performance and reduced board area: AD7626 in a 5 mm × 5mm, 32-lead LFCSP package, ADA4932-1 in a 3mm × 3mm, 16-lead LFCSP package), and AD8031 in a 5-lead SOT23 package.

Successfully driving an ADC using a differential amplifier requires correctly balancing the ends of the differential amplifier.

Figure 1 shows the schematic of the ADA4932-1, AD7626, and associated circuitry. In the test circuit used, the signal source is followed by a 2.4 MHz bandpass filter. The bandpass filter suppresses the harmonics of the 2.4 MHz signal and ensures that only signals at the frequency of interest pass through and are processed by the ADA4932-1 and AD7626.

The signal source in this example has a characteristic impedance of 50 Ω and is AC coupled to the ADA4932-1 through a bandpass filter. When applying a signal source to the positive input of the ADA4932-1, it is required that the signal source is also properly terminated at 50 Ω (generally any source impedance will do). Termination resistor R2 is selected so that the parallel combination of R2 and the input impedance of the ADA4932-1 equals 50 Ω. The calculation formula for the input impedance of ADA4932-1 (observing resistor R3) is as follows:

Where RG = R3 = R5 = 499 Ω, RF = R6 = R7 = 499 Ω. Based on these values, the input impedance of this circuit is approximately 665 Ω. The input impedance of ADA4932-1 is 50 Ω (that is, the input source impedance) when connected in parallel with the resistance of R2 of 53.6 Ω.

To maintain proper balance and symmetry between the two inputs of the ADA4932-1, a Thevenin impedance and a terminal impedance equivalent to the input source impedance must be added to the inverting input. In this case, the AC characteristics of the filter are involved.

As shown in Figure 1, the Thevenin equivalent network is shown at the inverting input of the ADA4932-1. The performance of this circuit is optimized at 2.4 MHz. After C1 and R4 are combined in series, they are connected in parallel with resistor R1. At a frequency of 2.4 MHz, the composite series combination of C1 and R4 equals 55.6 Ω. The 55.6 Ω impedance in parallel with R1 is only a few ohms different from the input impedance of the Thevenin equivalent circuit at the non-inverting input. Matching of both inputs ensures the output is symmetrical, balanced and optimized for lowest distortion.

For a detailed description of single-ended input termination methods, see application note AN-1026 "High-Speed ​​Differential ADC Driver Design Considerations . " In addition, Analog Devices' DiffAmpCalcuator™ design tool greatly simplifies this operation and provides unique insights into other issues related to differential amplifier design.

The ADA4932-1 differential driver is configured for a gain of approximately 1 (single-ended input to differential output). Due to the 50 Ω signal source and the matched terminal impedance at the ADA4932-1 input, the net total gain of the channel is approximately 0.5 relative to the Thevenin equivalent source voltage.

The common-mode voltage at the ADA4932-1 output can be set by buffering the AD7626's VCM output voltage (nominal +2.048 V) using the AD8031 configured as a unity-gain buffer. The AD8031 provides low source impedance to the ADA4932-1 VOCM pin and can drive large bypass capacitors, as shown in Figure 1.

The ADA4932-1 is particularly useful when driving the high-frequency input of the AD7626, a 10 MSPS ADC with switched capacitor inputs. The resistor (R8, R9) and capacitor (C5, C6) circuit between the IN+ and IN- pins of the ADA4932-1 and AD7626 acts as a low-pass noise filter. This filter limits the input bandwidth of the AD7626, but its main function is to optimize the interface between the driver amplifier and the AD7626. The series resistor isolates the driver amplifier from the high-frequency switching spikes in front of the ADC's switched capacitor. The AD7626 data sheet shows values ​​of 20 Ω and 56 pF. In the circuit shown in Figure 1, these values ​​are optimized for the actual application to 33 Ω and 56 pF. To slightly optimize the resistor-capacitor combination for the circuit and input frequency being converted, simply change the RC combination. However, remember that improper combination will limit the total harmonic distortion (THD) and linearity performance of the AD7626. In addition, the increase in ADC bandwidth will cause more noise.

The selection of the ADA4932-1 supply voltage has also been optimized. In the circuit, corresponding to the internal reference voltage of 4.096V, the output common mode voltage of the AD7626 (VCM pin) is 2.048 V, and each input (IN+, IN-) swings between 0 V and +4.096 V, which occurs 180° out of phase, this provides an 8.2 V full-scale differential input to the ADC. The ADA4932-1 output stage requires approximately 1.4 V of headroom for each supply voltage for linear operation. Best distortion performance is achieved when the supply voltage is approximately symmetrical about the common-mode voltage. If a -2.5 V negative supply is selected, then at least approximately +6.5 V positive supply is required to be symmetrical about the 2.048V common-mode voltage.

Experiments have shown that a +7.25 V positive supply provides the best total distortion performance for a 2.4 MHz tone.

Using a low-jitter clock source and the AD7626's single-tone -1 dBFS amplitude 2.402 MHz input produces the FFT results shown in Figure 2: a signal-to-noise ratio of 88.49 dB and a total harmonic distortion of -86.17 dBc. As can be seen from the figure, the harmonics of the fundamental wave are re-aliased into the passband. For example, at a sampling rate of 10 MSPS, the third harmonic (7.206 MHz) will alias into the passband at 10.000 MHz - 7.206 MHz = 2.794 MHz. Figure 3 shows the second FFT plot of a -6 dBfs amplitude signal tone.

When calculating the signal-to-noise ratio and total harmonic distortion, the non-harmonic noise allowed to pass by the passband of the bandpass filter used in the circuit is replaced by the average noise across the Nyquist bandwidth. The performance of this or any high-speed circuit is highly dependent on proper PCB layout, including but not limited to power supply bypassing, controlled impedance traces (if required), component placement, signal routing, and power and ground planes. (For more information on PCB layout, see the MT-031 Tutorial , MT-101 Tutorial , and the Practical Guide to High-Speed ​​Printed Circuit Board Layout article.)

AD7626—Typical Connections and Reference Voltage Configuration

A typical connection diagram of the AD7626 is shown in Figure 4. The AD7626 integrates an internal voltage reference and can provide two external voltage references based on system requirements. Applying the ADR280 reference output (1.2 V) to the REFIN pin generates a reference voltage that is internally amplified by the on-chip reference voltage buffer to the correct ADC reference voltage of 4.096 V. The ADR280 can be powered from the same 5 V analog supply rail used for the AD7626, while using the on-chip reference voltage buffer. Alternatively, a 4.096 V external reference voltage ( ADR434 or ADR444 ) can be applied to the unbuffered REF input of the ADC. This practice is common in multi-channel applications where the system reference voltage is usually buffered discretely (using the AD8031) and shared by all ADC channels. The ADR434 and ADR444 configurations are also ideal for single-channel applications that require a low reference temperature coefficient (3 ppm/°C maximum for the ADR434B and ADR444B). The positive rail used to power the ADA4932-1 amplifier can also power the VIN supply pin of the ADR434 or ADR444.