This circuit is a complete implementation of the analog part of a broadband direct conversion transmitter (analog baseband input, RF output). This circuit supports RF frequencies ranging from 500 MHz to 4.4 GHz through the use of a phase-locked loop (PLL) and a wideband integrated voltage-controlled oscillator (VCO). The LO in the PLL performs harmonic filtering, ensuring excellent quadrature accuracy.

Low-noise LDOs ensure that the power management scheme has no adverse impact on phase noise and EVM. This combination of devices provides industry-leading direct conversion transmitter performance from 500 MHz to 4.4 GHz.

The circuit shown in Figure 1 uses a fully integrated fractional-N PLL IC ADF4350 and a wideband transmit modulator ADL5375 . The ADF4350 provides the local oscillator (LO) signal to the transmit quadrature modulator ADL5375, which upconverts the analog I/Q signal to an RF signal. Together, the two devices provide a wideband baseband I/Q to RF transmit solution. The ADF4350 is powered by an ultralow noise 3.3 V ADP150 regulator for optimal LO phase noise performance. The ADL5375 is powered by a 5 V ADP3334 LDO. The ADP150 LDO's output voltage noise is only 9 μV rms, helping to optimize VCO phase noise and reduce the effects of VCO pushing (equivalent to power supply rejection).

The ADF4350 RF output needs to be filtered to attenuate the harmonic levels and minimize the error of the ADL5375 quadrature generation module. According to measurements and simulations, it is known that odd-order harmonics contribute more to quadrature error than even-order harmonics; if odd-order harmonics are attenuated below −30 dBc, sideband suppression performance of −40 dBc or better can be achieved . The ADF4350 data sheet gives its second harmonic (2H) and third harmonic (3H) levels, as shown in Table 1. To keep the third harmonic below -30 dBc, approximately C1c needs to be placed to minimize circuit board space. To attenuate 20 dB.

This circuit offers four different filter options to suit four different frequency bands. These filters are designed for 100 Ω differential input (ADF4350 RF output with appropriate matching) and 50 Ω differential output (ADL5375 LOIN differential impedance) and use a Chebyshev response for optimal filter roll-off but channel ripple. The waves will increase.

The filter schematic is shown in Figure 1. This topology is flexible and can use a fully differential filter to minimize component count, a single-ended filter for each output, or a combination of the two. We found that for higher frequencies (>2 GHz), the series inductance value of two single-ended filters is twice the inductance value of a fully differential filter, thus reducing the impact of device parasitics and providing optimal performance. For lower frequencies (<2 GHz), fully differential filters are sufficient.

The ADF4350 output matching includes the Z _BIAS pull-up resistor, and the decoupling capacitor of the power node also plays a role. To achieve broadband matching, it is recommended to use a resistive load (Z _BIAS = 50 Ω) ) or to connect a resistive load to Z _BIAS . It is recommended to use a resistive load (Z BIAS = 50 Ω) or to connect a resistive load to Z BIAS Reactive loads are connected in parallel. The latter provides slightly higher output power, depending on the inductor chosen. Note that the parallel resistor can be placed as a differential component (i.e. 100 Ω) in a location that minimizes board space. This is the case for the type c filter in Table 2.

Parasitic effects often cause the cutoff frequency to be lower than the design value, so the design cutoff frequency of the filter should be about 1.2 to 1.5 times the highest frequency in the target frequency band, leaving a certain margin. PCB parasitics can be simulated in EM simulation tools to improve accuracy.

As can be seen from Table 2, at lower frequencies below 1250 MHz, a fifth-order filter is required. For frequencies from 1.25 GHz to 2.8 GHz, a third-order filter is sufficient. For frequencies above 2.8 GHz, filtering is not required because the harmonic levels are very low and sufficient to meet sideband suppression requirements.

For a circuit using filter b (850 MHz to 2450 MHz), the sideband suppression performance versus frequency is shown in Figure 4. The test conditions for this frequency sweep are as follows: baseband I/Q amplitude = 1 V peak-to-peak differential sine wave, quadrature with 500 mV (ADL5375-05) DC bias; baseband I/Q frequency (fBB) = 1 MHz.

Error vector magnitude (EVM) is a measure of the performance quality of a digital transmitter or receiver, reflecting the deviation of actual constellation points from their ideal positions caused by amplitude and phase errors. The EVM diagram is shown in Figure 5.

Table 3 shows the EVM measurement results with and without filter. In this example, the baseband I/Q signals are generated using 3GPP test model 4 using a Rhode & Schwarz AMIQ (digital output) and an external 16-bit DAC board (AD9788). Additionally filter b is used. Figure 6 Block diagram of the EVM test setup.

Adjacent channel leakage ratio (ACLR) measures the relationship between the power of adjacent channels and the power of the main channel, expressed in dBc.

LO phase noise and modulator linearity are the main factors affecting ACLR. The ACLR test setup is roughly the same as the EVM test setup, except that the coaxial filter is located at the I/Q output of the AD9788 DAC board to reduce aliasing products.

Driving the ADL5375 LO input differentially provides performance benefits in addition to improved sideband rejection and EVM. Modulator OIP2 performance can be improved by 2dB to 5dB compared to single-ended LO drive. Note that most external VCOs only provide single-ended outputs, so using a differential output with the ADF4350 is preferable to using an external VCO. Figure 7 shows the sideband suppression results using an 850 MHz to 2450 MHz filter (Filter b).

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