encryption switch

This circuit requires a specific "decryption" signal to maintain the output terminal in a low level state, otherwise the output terminal is in a high level state;

This circuit uses two operational amplifiers to operate as a voltage comparator. The N-type field effect transistor outputs a high level and a theoretical current of 5A. The output voltage is close to the power supply voltage.

principle:

Comparator threshold: Two operational amplifiers are used as voltage comparators. The reverse input terminals of U1 and U2 use resistor voltage dividing (R1, R2 and R8, R9) to set the threshold voltage (two identical voltage dividing circuits are used in the schematic diagram , in fact, it is enough to share one voltage divider) C1 and C4 are the voltage dividing point filter capacitors.

U1 same-direction input terminal charging circuit: R3 and R4 form a voltage dividing circuit. R3 is also a current-limiting resistor and slowly charges C3. When the voltage of C3 is greater than the reverse input terminal of U1, U1 outputs a high level.

U1 non-directional input terminal discharge circuit: R5 and Q1 form a discharge circuit. R5 limits the discharge current. Assuming that U1 non-directional input terminal charging voltage is not greater than the threshold of U1 reverse input terminal, Q1 is turned on to discharge it, then U1 can always Keep the output low.

U2 same-direction input terminal charging circuit: R10, Q2, R11 form a voltage dividing charging circuit. R10 is also a current-limiting resistor. Q2 acts as a switch to slowly charge C5. When the voltage of C5 is greater than the reverse input terminal of U2, U2 outputs a high level. .

U2 non-directional input terminal discharge circuit: Assume that when the charging voltage of U2 non-directional input terminal is not greater than the threshold of U2 reverse input terminal, Q2 is turned off to stop charging. At this time, R11 becomes a discharge resistor to discharge C5, then U2 can always Keep the output low.

The output terminals of U1 and U2 use diode isolated parallel outputs to drive Q3 as the output. R14 is the gate current limiting resistor. The R15 gate pull-down resistor determines the gate state of Q3. R16 is the output pull-down resistor. Q3 is pulled low when it is not conducting. Output terminal, i.e. low level

Encryption and decryption principle:

The gates of Q1 and Q2 are connected in parallel as the decryption signal input terminal. When the input is high, Q1 and Q2 are turned on at the same time. Q1 discharges U1, making its non-directional input terminal voltage lower than the reverse input terminal. Q2 charges the non-directional input terminal of U2. , if the signal is always high level, then the voltage of the same input terminal of U1 is always pulled low, and U1 always outputs low level, there is no problem. However, Q2 will always be turned on to continue charging the same input terminal of U2 until the voltage is greater than the reverse input terminal and U2 outputs a high level. This is not possible. We need the output terminals of U1 and U2 to remain low at the same time. Then you need to remove the high-level signal in time when the discharge of the same-direction end of U1 is completed, so that Q2 is turned off and no longer charges the same-direction end of U2. Then U2 can also maintain a low-level output. When the high-level signal is removed, Q1 is cut off. In the discharge circuit of U1, the same direction end of U1 starts to charge again. At this time, we need to continue to use the high level signal to discharge the same direction end of U1. In this cycle, we need "high,, low,, high" ,,low,,high,,low,," decryption signal . At the same time, the high-level signal cannot exist for too long, otherwise the capacitor at the same direction end of U2 will be fully charged and U2 will output a high level, which is correct for There are requirements for the pulse width of the decrypted signal. The charging speed of U1 and the discharging speed of U2 have requirements on the frequency of the decryption signal. If the frequency is too slow, the same-direction end of U1 has been charged. If the frequency is too fast, the same-direction end of U2 has not completed the discharge and starts charging again. The result is The capacitor remains fully charged after a certain number of charges.

Decrypted signal of this schematic circuit: PWM square wave 2HZ pulse width <30%

Proofing has been verified! ! !