Lanqiao Cup EDA Competition Design and Development Subject Design Part 1 Training Questions
(Provided by Lichuang EDA, for training purposes only)
Create a new component package and name it: LQ-DIP-40. The package design requirements are shown in the figure below. (5 points)
Figure 1 Package design (LQ-DIP-40)
Design requirements:
New Construction;
Open the schematic file sch.json provided in the "Resource Data Package"; complete the schematic design according to the following requirements.
1. According to the sample diagram given, complete the placement of component symbols, line drawing and network addition in the buzzer driver circuit design area (Buzzer Driver). (12 points)
Figure 2 Digital tube drive circuit
Design requirements
2. In the LED design area (LED Drivers), according to the given circuit connection relationship, calculate the values of resistors R12 and R13 (assuming VF is 2V and the conduction current is 15mA), and fill in the calculation results into the R12 and R13 components in the name of the attribute. (8 points)
Schematic design description:
Component numbers |
encapsulation |
B1 |
BUZ-TH_BD12.0-P7.60-D0.6-FD |
C1, C3 |
CAP-TH_BD5.0-P2.00-D0.8-FD |
C2, C5 |
CAP-TH_L7.0-W3.0-P5.00-D0.9 |
C4 |
CAP-TH_L5.0-W2.5-P2.54-D0.7 |
C6, C7 |
C0805 |
D1~D8 |
LED0805_BLUE |
J1, J2 |
HDR-M-2.54_1X20 |
KEY1~KEY4,RST |
KEY-SMD_4P-L6.0-W6.0-P3.90-LS10.0 |
L1 |
DO-35_BD2.0-L4.0-P8.00-D0.5-FD |
LCD1 |
LCD1602 |
LED1 |
LED-TH_BD3.0_BLUE |
LED2 |
LED-TH_BD3.0_GREEN |
LED3 |
LED0805_BLUE |
LED4 |
LED0805_GREEN |
LED5 |
LED-TH_BD3.0_RED |
Q1 |
TO-92-3_L4.9-W3.7-P1.27-L |
R1, R2, R11, R12, R13, R16 |
RES-TH_BD2.4-L6.3-P10.30-D0.6 |
R3~R10, R114, R15 |
R0805 |
RN1 |
RES-ARRAY-TH_9P-P2.54-D1.0 |
RP1 |
RES-ADJ-TH_3296W |
SW1 |
SW-TH_SS-12D02-VG4 |
U1 |
SENSOR-TH_DHT11 |
U2 |
DIP-40_L52.0-W13.7-P2.54-LS15.2-BL |
U3 |
SOIC-16_L9.9-W3.9-P1.27-LS6.0-BL |
U4 |
SOP-16_L10.0-W3.9-P1.27-LS6.0-BL |
USB1 |
MICRO-USB-SMD_5P_C40957 |
X1 |
HC-49US_L11.5-W4.5-P4.88 |
Note: All package libraries are searched and bound in the library list of Lichuang Mall.
Reasonably arrange the layout. Components should be arranged parallel or vertically to each other in order to be neat and beautiful. Overlapping of components is not allowed. The arrangement of components should be compact, and the components should be evenly distributed and dense throughout the entire layout.
Minimum line width: ≥14mil Line spacing: ≥6mil
Via size: 20mil/40mil Number of wiring layers: 2
Character layer: The top silk screen layer requires the characters to be placed neatly. Copper layer: top layer, bottom layer, GND network.
Cloth rate: 100%
Export the netlist from the schematic (Free PCB format) and rename it to USER.net.
1. Complete the design of the LQ-DIP-40 package according to the design requirements of the first library file of the test question, export the Lichuang EDA package library file, and name it LQ-DIP-40.json.
2. According to the schematic design requirements of question 2, complete the drawing of the schematic diagram, export the EasyEDA schematic diagram file, and name it SCH.json.
3. Complete the PCB design according to the PCB design requirements of question three, export the EDA PCB file, and name it PCB.json; export the netlist file (Free PCB format) to USER.net.
4. The compressed file package finally uploaded by the contestant should contain four files: LQ-DIP-40.json, SCH.json, PCB.json, and USER.net.
5. Contestants who fail to name and submit documents as required will have their points deducted or zero points as appropriate. Contestants who submit documents that do not meet the test question requirements will have their points deducted as appropriate.
Video teaching materials: https://www.bilibili.com/video/BV1LP4y1E7Hd?p=4
Test question package: Please download it from the attachment.
All reference designs on this site are sourced from major semiconductor manufacturers or collected online for learning and research. The copyright belongs to the semiconductor manufacturer or the original author. If you believe that the reference design of this site infringes upon your relevant rights and interests, please send us a rights notice. As a neutral platform service provider, we will take measures to delete the relevant content in accordance with relevant laws after receiving the relevant notice from the rights holder. Please send relevant notifications to email: bbs_service@eeworld.com.cn.
It is your responsibility to test the circuit yourself and determine its suitability for you. EEWorld will not be liable for direct, indirect, special, incidental, consequential or punitive damages arising from any cause or anything connected to any reference design used.
Supported by EEWorld Datasheet