EP4CGX150 core board

Note: Today's FPGA chips are very expensive. I searched for it on Xianyu for a long time and finally found this relatively cheap chip, which costs about 50 yuan. This is the only one under a hundred dollars. . . . .
As long as there is a heating table, the BGA package is still easy to solder. Although the first soldering failed, the second soldering was successful.
The attachment is the official source code. You can study it yourself. After all, this topic is a bit old.
1. The question requires that
this design mainly belongs to the soft core design of IP core. The soft core includes logic description, device internal connection table and incompatible Design for testability performed externally. The soft core can be modified by the user to implement the required circuit system. It is mainly used for complex systems with a wide range of speed performance requirements such as interfaces, encoding, decoding, algorithms and channel encryption.
2. Problem analysis
This article uses Intel's Tornado 4 series FPGA chip, and with the support of the EDA software platform, designs the 8051 chip based on FPGA. Based on the published 8051 source code, the design area is reduced and the processing speed is improved. This design is written in ultra-high-speed integrated circuit hardware description language (VHDL), and functional simulation is performed using Modelsim. Through the existing 51 series microcontroller development environment Keil, the 51 code is combined into the FPGA for synthesis, and finally downloaded to the FPGA. In the chip, physical verification was performed, and the results showed that the soft core achieved the expected results.
3. Overall scheme design diagram
4. Schematic design description
The FPGA chip model is EP4CGX150DF27I7. The chip is mainly characterized by low cost and low power consumption. It has 150,000 logic units, up to 360 18×18 multipliers, and 4 general-purpose PLLs. , 8 global clock networks, up to 6.4M embedded memory, realizing DSP processing intensive, the maximum available IO ports can reach 475; EP4CGX150DF27I7 adopts the core board design in this design, which is conducive to secondary development And debugging, it can also find problems more conveniently.
Since there is no internal crystal driver inside the FPGA chip like a microcontroller, the FPGA uses an active crystal oscillator. The active crystal oscillator does not require the internal oscillator of the target chip, which not only reduces the number of pins used by the chip, but also improves the stability of the frequency output. sex.
Cyclone IV GX FPGA requires three sets of power supplies, namely core power supply, PLL analog circuit power supply and IO unit power supply. The FPGA core power supply is 1.2V. This design uses a DC-DC power supply. The TPS564201 step-down type is used to design the conversion circuit. Compared with a linear regulator, it can provide a larger current when the voltage is stable.
The program memory is Flash, model number is W25Q128, and the storage capacity is 16Mbit. Compared with EPROM, FLASH has a larger storage capacity. The SPI protocol is used to realize communication between the FPGA chip and the Flash memory. The Flash has the characteristic of not losing data when power is turned off. Connect the D5, D6, E5 and E6 pins of the FPGA to the storage module, and then store the program in Flash. After the FPGA is powered on, it can directly run the program in the Flash to ensure that the program is not lost after the FPGA is powered off.
5. Code Description
The arithmetic logic unit is a pure combinational logic and does not require a clock signal. It covers the arithmetic operations of addition, subtraction, multiplication and division, as well as AND, OR, XOR, comparison, negation and shift operations.
The central controller is an indispensable core of the microcontroller and the heart of the microcontroller. Its main function is to process data from other modules. The central controller is mainly composed of the finite state machine FSM and the control memory MEM. The
two 16-bit timer/counters T0 and T1 set inside the traditional 51 series microcontroller have two working modes: counting mode and timing mode. For each timer/counter, there are control bits in the special function register TMOD to select T0 or T1 as a timer or its summer. In order to facilitate simple debugging in this design, the function of the timer/counter is not multiplexed with the IO port. Instead, the input control of the timer/counter is used as an IO port alone. Working mode 0 is a 13-bit timer/counter, working mode 1 is a 16-bit timer/counter, working mode 2 is an 8-bit automatic reload timer/counter, eliminating the need to manually reload the initial counting value in mode 0 and mode 1. . Working mode 3 is only applicable to timer T0.
In order to facilitate the design, the serial port is not multiplexed with the 8051IO port, but becomes an independent serial interface. There are two independent receiving and sending buffers, which can send and receive data at the same time. The two buffers are collectively called the serial communication special function register SBUF. The serial port has four working modes, two of which have variable baud rates and the other two are fixed for selection in different applications. The baud rate is generated by the internal timer/counter, and software is used to set different baud rates and select different working modes.
ROM and RAM can be instantiated through the software's integrated MegaWizard plug-in manager, SOPC constructor or DSP constructor, and Qsys design system.
6. Test instructions:
synthesize each module, lock the pins, load the hex file compiled by keil into the generated ROM, capture the waveform through the Signaltap that comes with the Quartus software, configure the Signaltap file, recompile and download to the board , click Run, and you can see the waveform.
6.PCB diagram