The difference between cpld and fpga

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The difference between cpld and fpga [Copy link]

Systematic comparison, shared with you: Although FPGA and CPLD are both programmable ASIC devices with many common features, they have their own characteristics due to the differences in the structures of CPLD and FPGA: ① CPLD is more suitable for completing various algorithms and combinational logic, while FPGA is more suitable for completing sequential logic. In other words, FPGA is more suitable for structures with rich triggers, while CPLD is more suitable for structures with limited triggers and rich product terms. ② The continuous wiring structure of CPLD determines that its timing delay is uniform and predictable, while the segmented wiring structure of FPGA determines the unpredictability of its delay. ③ In terms of programming, FPGA has greater flexibility than CPLD. CPLD is programmed by modifying the logic function with fixed internal circuits, while FPGA is mainly programmed by changing the wiring of internal connections; FPGA can be programmed under logic gates, while CPLD is programmed under logic blocks. ④ FPGA has a higher integration level than CPLD, and has a more complex wiring structure and logic implementation. ⑤ CPLD is more convenient to use than FPGA. CPLD programming adopts E2PROM or FASTFLASH technology, does not require external memory chip, and is simple to use. However, the programming information of FPGA needs to be stored in external memory, and the method of use is complicated. ⑥ CPLD is faster than FPGA and has greater time predictability. This is because FPGA is gate-level programming, and the CLBs are connected in a distributed manner, while CPLD is logic block-level programming, and the connections between its logic blocks are lumped. ⑦ In terms of programming method, CPLD is mainly based on E2PROM or FLASH memory programming, and the number of programming times can reach 10,000 times. The advantage is that the programming information will not be lost when the system is powered off. CPLD can be divided into two categories: programming on the programmer and programming in the system. Most FPGAs are based on SRAM programming. The programming information is lost when the system is powered off. Each time the power is turned on, the programming data needs to be rewritten into the SRAM from the outside of the device. Its advantages are that it can be programmed any number of times and can be programmed quickly during work, thus achieving dynamic configuration at the board level and system level. ⑧CPLD has good confidentiality, while FPGA has poor confidentiality. ⑨Generally speaking, the power consumption of CPLD is greater than that of FPGA, and the higher the integration, the more obvious it is. With the increase in the density of complex programmable logic devices (CPLDs), digital device designers are both flexible and easy when carrying out large designs, and their products can enter the market quickly. Many designers have already experienced the advantages of CPLDs such as ease of use, predictable timing, and high speed. However, in the past, due to the limitations of CPLD density, they had to turn to FPGAs and ASICs. Now, designers can experience the benefits of CPLDs with densities as high as hundreds of thousands of gates. The CPLD structure uses 1 to 16 product terms in a logic path, so the running speed of large and complex designs can be predicted. Therefore, the operation of the original design is predictable and reliable, and it is easy to modify the design. CPLD is flexible in nature, has simple timing, and excellent routing performance, and users can change their designs while keeping the pinout unchanged. Compared with FPGA, CPLD has more I/O and smaller size. Today, communication systems use many standards, and equipment must be configured according to customer needs to support different standards. CPLD allows equipment to make corresponding adjustments to support multiple protocols and change functions as standards and protocols evolve. This brings great convenience to system designers because they can start hardware design before the standard is fully mature, and then modify the code to meet the requirements of the final standard. The speed and delay characteristics of CPLD are better than pure software solutions, its NRE cost is lower than ASIC, it is more flexible, and products can be put on the market faster. The advantages of CPLD programmable solutions are as follows: ● Rich logic and memory resources (Cypress Delta39K200 has more than 480 Kb of RAM) ● Flexible timing model with redundant routing resources ● Very flexible to change pinout ● Can be reprogrammed after installation on the system ● Large number of I/Os ● Integrated memory control logic with guaranteed performance ● Single-chip CPLD and programmable PHY solutions are available Because of these advantages, the design modeling cost is low, and the design can be added or the pinout can be changed at any stage of the design process, and it can be quickly put on the market CPLD structure CPLD is a coarse-grained programmable logic device. It has rich logic resources (i.e., a high ratio of logic gates to registers) and highly flexible routing resources. The routing of CPLD is connected together, while the routing of FPGA is separated. FPGA may be more flexible, but includes many jumpers, so the speed is slower than CPLD. CPLD is arranged in the form of an array of clusters, connected by horizontal and vertical routing channels. These routing channels send signals to or from the pins of the device and connect the logic groups inside the CPLD. CPLDs are called coarse-grained because the logic groups are large compared to the number of routes. CPLDs have much larger logic groups than the basic cells of FPGAs, so FPGAs are fine-grained. Functional Blocks of CPLDs The most basic unit of a CPLD is the macrocell. A macrocell contains a register (using up to 16 product terms as its inputs) and other useful features. Because each macrocell uses 16 product terms, designers can implement a large amount of combinational logic without adding additional paths. This is why CPLDs are considered "logic-rich". Macrocells are arranged in logic blocks (LBs), and each logic block consists of 16 macrocells. Macrocells perform an AND operation and then an OR operation to implement combinational logic. Each logic group has 8 logic blocks, and all logic groups are connected to the same programmable interconnect matrix. Each group also contains two single-port logic group memory blocks and one multi-port channel memory block. The former has 8,192b of memory per block, and the latter contains 4,096b of dedicated communication memory and can be configured as single-port, multi-port, or FIFO with dedicated control logic. What are the benefits of CPLDs? High I/O Counts One benefit of CPLDs is that they provide more I/Os for a given device density, sometimes up to 70%. Simple Timing Models CPLDs are superior to other programmable architectures in that they have simple and predictable timing models. This simple timing model is primarily due to the coarse-grained nature of CPLDs. CPLDs can provide a wide range of equal states in a given time, regardless of routing. This capability is key to design success, speeding up not only initial design work but also the design debugging process. Advantages of Coarse-Grain CPLD Architecture CPLDs are coarse-grained, which means that the paths in and out of the device pass through fewer switches and, accordingly, have less delay. As a result, CPLDs can operate at higher frequencies and have better performance than equivalent FPGAs. Another benefit of CPLDs is that their software compiles quickly because their easy-to-route architecture makes the task of laying out the design easier to perform. Advantages of Fine-Grain FPGA Architecture FPGAs are fine-grained, which means that there are fine-grained delays between each cell. FPGAs are quite fast if small amounts of logic are packed closely together. However, as the design density increases, the signal has to pass through many switches, and the routing delay increases rapidly, thus weakening the overall performance. The coarse-grained structure of the CPLD can adapt well to this change in design layout. Flexible output pins The coarse-grained structure and timing characteristics of the CPLD are predictable, so designers can still change the output pins in the later stage of the design process while the timing remains unchanged. New CPLD Package CPLD has a variety of densities and package types, including a single-chip self-boot solution. The self-boot solution integrates FLASH memory and CPLD in a single package, eliminating the need for an external boot unit, thereby reducing design complexity and saving board space. Within a given package size, there is a higher device density sharing pin output. This provides designers with the convenience of "enlarging" the design without changing the pin output on the board.

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