How to Choose the Right MOSFET for Hot Swapping

1. Introduction

When a power source is suddenly disconnected from its load, the large current swings across the circuit’s parasitic inductive elements can create dramatic voltage spikes that can be harmful to the electronic components on the circuit. Similar to the battery protection application, here the MOSFET is used to isolate the input power source from the rest of the circuit. However, in this case, the FET is not meant to instantly cut the connection between the input and output, but to limit the severity of those damaging current surges. This is accomplished by the controller regulating the voltage between the input supply (V IN ) and the output voltage (V OUT ) to force the MOSFET to operate in saturation mode, thereby hindering the amount of current that can pass (see Figure 1). 

Figure 1: Simplified hot-swap circuit

2. Selecting MOSFETs for hot swapping

First, our first consideration for this FET should be choosing an appropriate breakdown voltage, which is typically 1.5 to 2 times the maximum input voltage. For example, 12V systems tend to implement 25V or 30V FETs, while 48V systems tend to implement 100V or in some cases 150V FETs. The next consideration should be the safe operating area (SOA) of the MOSFET - a curve provided in the datasheet is particularly useful and can be used to indicate how sensitive the MOSFET is to going into thermal runaway during a short power surge, which is different from the surge it must absorb in a hot-swap application.

As a designer, the key question we ask is what is the maximum current surge the FET might see (or be expected to limit at the output), and how long that surge will last. Once this is known, it is relatively simple to look up the corresponding current and voltage differences on the SOA graph in the device datasheet.

For example, if our design has a 48V input and we want to limit the output current to no more than 2A for 8ms, we can refer to the 10ms curves for the CSD19532KTT, CSD19535KTT, and CSD19536KTT SOA (Figure 2) and infer that the latter two devices will probably work, while the CSD19532KTT will not. But since the CSD19535KTT is good enough with some margin, the performance of the more expensive CSD19536KTT may be overkill for this application. 

Figure 2: SOA of three different 100V D2PAK MOSFETs

In the example above, I assumed an ambient temperature of 25˚C, the same conditions under which the SOA is measured on the datasheet. However, if the end application may be exposed to a hotter environment, the SOA must be derated proportionally based on how close the higher ambient temperature is to the maximum junction temperature of the FET. For example, assume the maximum ambient temperature of the end system is 70˚C; we can derate the SOA curve using Equation 1:

Selecting MOSFETs for Hot Swap

In this case, the 10ms, 48V capability of the CSD19535KTT would be reduced from ~2.5A to ~1.8A. We would then conclude that this particular FET may no longer be adequate for this application and choose the CSD19536KTT instead.

It is important to note that this derating method assumes that the MOSFET will fail exactly at the maximum junction temperature, which is typically not the case. Suppose the failure point measured in the SOA test actually occurs at 200˚C or some other arbitrarily higher value; the calculated derating will be closer to unity. In other words, this derating method errs on the side of being conservative.

    The SOA will also dictate the type of MOSFET package we choose. D2PAK packages can accommodate large silicon dies, so they are ideal for higher power applications. Smaller 5mm x 6mm and 3.3mm x 3.3mm quad flat no-lead (QFN) packages are better suited for lower power applications. For surge currents less than 5 – 10A, FETs are most often integrated with a controller.

Some final warnings:

    While I’ve specifically discussed hot-swap applications here, we can apply the same SOA selection process to any situation where the FET is operating in the saturation region. We can even use the same approach to select FETs for slow switching applications such as OR-ing applications, Power over Ethernet (PoE), or even motor control where there is a lot of overlap in V DS and I DS during the MOSFET turn-off.

    Hot-swap is an application that tends to favor surface-mount FETs over through-hole FETs such as TO-220 or I-PAK packages. The reason is that the heating that occurs during short pulse durations and thermal runaway events is very localized. In other words, the capacitive thermal impedance element from the silicon junction to the case prevents the heat from dissipating into the board or heat sink quickly enough to cool the junction. Junction-to-case thermal impedance (R θJC ) is a function of die size and is important, but junction-to-ambient thermal impedance (R θJA ) is a function of the package, board, and system thermal environment and is less important. For the same reason, it is rare to see heat sinks used in these applications.

    Designers often assume that the lowest resistance MOSFET in a catalog will have the strongest SOA. There is some logic to this – lower resistance within the same generation of silicon usually indicates a larger silicon die within the package, which does yield greater SOA capabilities and lower junction-to-case thermal impedance. However, as silicon generations improve in terms of resistance per unit area (RSP), they tend to increase cell density. The denser the cell structure inside the silicon die, the more susceptible the chip is to thermal runaway. This is why older generation FETs with higher resistance sometimes also have better SOA performance. The bottom line is that it is always worth investigating and comparing SOA.