Bt8375KPF datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> Bt8375KPF

Bt8375KPF: DescriptionDATACOM, FRAMER, PQFP80; CategoryWireless rf/communication Telecom circuit; File Size2MB，323 Pages; ManufacturerCONEXANT; Websitehttp://www.conexant.com/; Related ProductsFound18parts with similar functions to Bt8375KPF

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Bt8375KPF Overview

DATACOM, FRAMER, PQFP80

Bt8375KPF Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	CONEXANT
Parts packaging code	QFP
package instruction	QFP, QFP80,.7SQ
Contacts	80
Reach Compliance Code	compli
JESD-30 code	S-PQFP-G80
JESD-609 code	e0
length	14 mm
Number of functions	1
Number of terminals	80
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP80,.7SQ
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	2.3 mm
Maximum slew rate	0.175 mA
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	FRAMER
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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Bt8370/8375/8376

Fully Integrated T1/E1 Framer and Line Interface

The Bt8370/8375/8376 is a family of single chip transceivers for T1/E1 and Integrated

Service Digital Network (ISDN) primary rate interfaces, operating at 1.544 Mbps or

2.048 Mbps. These devices combine a sophisticated framer, transmit and receive slip

buffers, and an on-chip physical line interface to provide a complete T1/E1 transceiver.

The fully featured Bt8370 and short-haul Bt8375 and Bt8376 devices provide a

programmable clock rate adapter for simplifying system bus interfacing. The adapter

synthesizes standard clock signals from the receive or transmit line rate clocks or from an

external reference.

Operations are controlled through memory-mapped registers accessible via a parallel

microprocessor port. Current ANSI, ETSI, ITU-T, and Bellcore standards are supported for

alarm and error monitoring, signaling supervision (e.g., LAPD/SS7), per-channel trunk

conditioning, and Facility Data Link (FDL) maintenance. A serial Time Division Multiplexed

(TDM) system bus interface allows the backplane Pulse Code Modulation (PCM) data

highway to operate at rates from 1.536 to 8.192 Mbps. Extensive test and diagnostic

functions include a full set of digital and analog loopbacks, PRBS test pattern generation,

BER meter, and forced error insertion.

The physical line interface circuit recovers clock and data from analog signals with +3 to

–43 dB cable attenuation, appropriate for both short (–18 dB) and long-haul T1/E1

applications. Receive line equalization (EQ) and transmit Line Build Out (LBO) filters are

implemented using Digital Signal Processor (DSP) circuits for reliable performance. Data

and/or clock jitter attenuation can be inserted on either the receive or transmit path. The

transmit section includes precision pulse shaping and amplitude pre-emphasis for cross

connect applications, as well as a set of LBO filters for long-haul Channel Service Unit

(CSU) applications. A complementary driver output is provided to couple 75/100/120

Ω

lines via an external transformer.

Distinguishing Features

•

Single-chip T1/E1 framer with

short/long-haul physical line

interface

Frames to popular T1/E1 standards:

– T1: SF, ESF, SLC



96, T1DM

– E1: PCM

30, G.704, G.706, G.732

ISDN primary rate

•

On-chip physical line interface

compatible with:

– DSX-1/E1 short-haul signals

– DS-1 (T1.403) and ETSI long-haul

signals

•

Functional Block Diagram

Two-frame transmit and receive PCM

slip buffers

Clock rate adapter synthesizes jitter

attenuated system clocks from an

internal or external reference

Parallel 8-bit microprocessor port

supports Intel or Motorola buses

Automated Facility Data Link (FDL)

management

BERT generation and counting

Two full-duplex HDLC controllers for

data link and LAPD/SS7 signaling

B8ZS/HDB3/Bit 7 zero suppression

80-pin MQFP surface-mount package

Operates from a single +5 Vdc ±5%

power supply

Low-power CMOS technology

Receive

Analog

RPLL

ZCS

Decode

TX or RX

Jitter

Attenuator

ZCS

Encode

Overhead

Insertion

T1/E1

Receive

Framer

Slip

Buffer

Receive

System

Bus

Applications

•

T1/E1 Channel Service Unit/Data

Service Unit (CSU/DSU)

Digital Access Cross-Connect

Systems (DACS)

T1/E1 Multiplexer (MUX)

PBXs and PCM channel bank

T1/E1 HDSL terminal unit

ISDN Primary Rate Access (PRA)

TPLL

Transmit

Analog

Pulse

LBO

Slip

Buffer

Transmit

System

Bus

T1/E1

Transmit

Framer

Clock Rate

Adaptor

•

JTAG

Control/Status

Registers

Data Link Controllers

DL1 + DL2

Test Port

Motorola/Intel

Processor Bus

Dual-Rail/NRZ/

External DL3

CLAD I/O

Data Sheet

N8370DSE

June 30, 1999

Table of Contents

List of Figures

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii

List of Tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

1.0

Pin Descriptions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1

Pin Assignments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

2.0

Circuit Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1

2.2

Bt8370/8375/8376 Block Diagrams

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Receive Line Interface Unit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.2.1

Data Recovery

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.1.1

Automatic Gain Control

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.1.2

Variable Gain Amplifier

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.1.3

Adaptive Equalizer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.1.4

Data Slicer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Clock Recovery

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.2.1

Phase Locked Loop

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.2

2.3

2.4

Jitter Attenuator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.3.1

Elastic Store

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Receiver

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.4.1

2.4.2

2.4.3

ZCS Decoder

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

In-Band Loopback Code Detection

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

Error Counters

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.4.3.1

Frame Bit Error Counter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.4.3.2

CRC Error Counter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.4.3.3

LCV Error Counter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.4.3.4

FEBE Counter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Error Monitor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.4.4

N8370DSE

Conexant

iii

Table of Contents

Bt8370/8375/8376

Fully Integrated T1/E1 Framer and Line Interface

2.4.5

2.4.6

2.4.7

2.4.8

2.4.9

2.4.10

Alarm Monitor

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.4.5.1

Loss of Frame

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.4.5.2

Loss of Signal

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.4.5.3

Analog Loss of Signal

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.5.4

Alarm Indication Signal

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.5.5

Yellow Alarm

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.5.6

Multiframe YEL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.5.7

Severely Errored Frame

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.5.8

Change of Frame Alignment

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.5.9

Receive Multiframe AIS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

Test Pattern Receiver

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

Receive Framing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

External Receive Data Link

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

Sa-Byte Receive Buffers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

Receive Data Link

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

2.4.10.1 Data Link Controllers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

2.4.10.2 RBOP Receiver

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31

Timebase

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35

Slip Buffer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36

Signaling Buffer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

Signaling Stack

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

Embedded Framing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38

2.5

Receive System Bus

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32

2.5.1

2.5.2

2.5.3

2.5.4

2.5.5

2.6

2.7

Clock Rate Adapter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39

2.6.1

Configuring the CLAD Registers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

Transmit System Bus

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46

2.7.1

2.7.2

2.7.3

2.7.4

2.7.5

Timebase

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48

Slip Buffer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48

Signaling Buffer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

Transmit Framing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

Embedded Framing

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52

External Transmit Data Link

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Transmit Data Links

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

2.8.2.1

Data Link Controllers

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

2.8.2.2

PRM Generator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

Sa-Byte Overwrite Buffer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

Overhead Pattern Generator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60

2.8.4.1

Framing Pattern Generation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60

2.8.4.2

Alarm Generator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60

2.8.4.3

CRC Generation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

2.8.4.4

Far-End Block Error Generation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

2.8

Transmitter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

2.8.1

2.8.2

2.8.3

2.8.4

Conexant

N8370DSE

Bt8370/8375/8376

Fully Integrated T1/E1 Framer and Line Interface

2.8.5

2.8.6

2.8.7

2.8.8

2.9

2.9.1

2.9.2

Table of Contents

Test Pattern Generator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Transmit Error Insertion

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64

In-Band Loopback Code Generator

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65

ZCS Encoder

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65

Pulse Shape

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

Transmit Phase Lock Loop

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76

2.9.2.1

Clock Reference

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76

2.9.2.2

Output Jitter

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77

Line Build Out

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77

Line Driver

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80

2.9.4.1

Termination Impedance

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80

2.9.4.2

Return Loss

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81

2.9.4.3

Output Enable

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82

Pulse Imbalance

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82

Address/Data Bus

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84

Bus Control Signals

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84

Interrupt Requests

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-84

Device Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85

2.10.4.1 Power-On Reset (POR)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85

2.10.4.2 Hardware Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85

2.10.4.3 Software Reset

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85

Remote Line Loopback

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86

Remote Payload Loopback

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86

Remote Per-Channel Loopbacks

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86

Local Analog Loopback

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87

Local Framer Loopback

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87

Local Per-Channel Loopback

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87

Instructions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88

Device Identification Register

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89

Transmit Line Interface Unit

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68

2.9.3

2.9.4

2.9.5

2.10.1

2.10.2

2.10.3

2.10.4

2.10 Microprocessor Interface

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83

2.11 Loopbacks

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86

2.11.1

2.11.2

2.11.3

2.11.4

2.11.5

2.11.6

2.12.1

2.12.2

2.12 Joint Test Access Group

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88

N8370DSE

Conexant

Bt8375KPF Related Products

	Bt8375KPF	BT8375	BT8376	Bt8376EPF	Bt8376KPF
Description	DATACOM, FRAMER, PQFP80	DATACOM, FRAMER, PQFP80	DATACOM, FRAMER, PQFP80	DATACOM, FRAMER, PQFP80	DATACOM, FRAMER, PQFP80
Is it lead-free?	Contains lead	-	-	Contains lead	Contains lead
Is it Rohs certified?	incompatible	-	-	incompatible	incompatible
Parts packaging code	QFP	-	-	QFP	QFP
package instruction	QFP, QFP80,.7SQ	-	-	QFP, QFP80,.7SQ	QFP, QFP80,.7SQ
Contacts	80	-	-	80	80
Reach Compliance Code	compli	-	-	compli	compli
JESD-30 code	S-PQFP-G80	-	-	S-PQFP-G80	S-PQFP-G80
JESD-609 code	e0	-	-	e0	e0
length	14 mm	-	-	14 mm	14 mm
Number of functions	1	-	-	1	1
Number of terminals	80	-	-	80	80
Maximum operating temperature	70 °C	-	-	85 °C	70 °C
Package body material	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	-	-	QFP	QFP
Encapsulate equivalent code	QFP80,.7SQ	-	-	QFP80,.7SQ	QFP80,.7SQ
Package shape	SQUARE	-	-	SQUARE	SQUARE
Package form	FLATPACK	-	-	FLATPACK	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	-	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	-	-	5 V	5 V
Certification status	Not Qualified	-	-	Not Qualified	Not Qualified
Maximum seat height	2.3 mm	-	-	2.3 mm	2.3 mm
Maximum slew rate	0.175 mA	-	-	0.175 mA	0.175 mA
Nominal supply voltage	5 V	-	-	5 V	5 V
surface mount	YES	-	-	YES	YES
technology	CMOS	-	-	CMOS	CMOS
Telecom integrated circuit types	FRAMER	-	-	FRAMER	FRAMER
Temperature level	COMMERCIAL	-	-	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	-	-	GULL WING	GULL WING
Terminal pitch	0.65 mm	-	-	0.65 mm	0.65 mm
Terminal location	QUAD	-	-	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	-	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	-	-	14 mm	14 mm

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