ICS525-01/02/11/12
User Configurable Clock
Description
The ICS525-01/02/11/12 are the most flexible way to
generate a high-quality, high-accuracy, high-frequency
clock output from an inexpensive crystal or clock input.
The user can configure the device to produce nearly
any output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked
Loop (PLL) techniques, the device accepts a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 250 MHz. It can also produce a
highly accurate output clock from a given input clock,
keeping them frequency locked together.
For similar capability with a serial interface, use the
ICS307. For simple multipliers to produce common
frequencies, refer to the ICS50x family of parts, which
are smaller and more cost effective.
These products are intended for clock generation. They
have low output jitter (variation in the output period), but
input to output skew and jitter are not defined nor
guaranteed. For applications which require defined
input to output timing, use the ICS527-01.
Features
•
Packaged as 28-pin SSOP (150 mil body)
•
Industrial and commercial versions available in Pb
(lead) free package
•
User determines the output frequency by setting all
•
•
•
•
•
•
•
•
•
•
•
•
internal dividers
Eliminates need for custom oscillators
No software needed
Online calculator determines register settings
Pull-ups on all select inputs
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Very low jitter
Duty cycle of 45/55 up to 200 MHz
Operating voltage of 3.0 V or 5.5 V
Ideal for oscillator replacement
Industrial temperature version available
For Zero Delay, refer to the ICS527
Block Diagram
2
PD
X1/ICLK
Crystal or clock
input
Crystal
Oscillator
X2
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Divider
CLK
VCO
Output
Divider
REF
VDD
Optional crystal capacitors
7
R6:R0
9
V8:V0
2
GND
3
S2:S0
MDS 525-01/02/11/12 Q
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
ICS525-01/02/11/12
User Configurable Clock
Pin Assignment
R5
R6
S0
S1
S2
VDD
X1/ICLK
X2
GND
V0
V1
V2
V3
V4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R3
R2
R1
R0
VDD
REF
CLK
GND
PD
V8
V7
V6
V5
ICS525-01/-02/-11/-12
Pin Descriptions
Pin
Number
1, 2,
24-28
3, 4, 5
6, 23
7
8
9, 20
10 - 18
19
21
22
Pin
Name
R5, R6,
R0-R4
S0, S1, S2
VDD
X1/ICLK
X2
GND
V0 - V8
PD
CLK
REF
Pin
Type
I(PU)
I(PU)
Power
X1
X2
Power
I(PU)
Input
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number from 0
to 127.
Select pins for output divider determined by user. See table on page 3
Connect to VDD.
Crystal connection. Connect to a parallel resonant fundamental crystal or input clock.
Crystal connection. Connect to a crystal or leave unconnected for clock.
Connect to ground.
VCO divider word input pins determined by user. Forms a binary number from 0 to
511.
Power-down. Active low. Turns off entire chip when low. Clock outputs stop low.
Output clock determined by status of R0-R6, V-V8, S0-S2, and input frequency.
Reference output. Buffered crystal oscillator (or clock ) output.
KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections
MDS 525-01/02/11/12 Q
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
ICS525-01/02/11/12
User Configurable Clock
ICS525-01 Output Frequency and Output Divider Table
S2
S1
S0 CLK Output
Pin 5 Pin 4 Pin 3
Divider
Output Frequency Range (MHz)
VDD = 5 V
0 - 70
°C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
2
8
4
5
7
9
6
3–26
15–160
3.75–40
7.5–80
6–50
4–40
3.3–33.3
5–53
-40 to +85
°C
3–23
15–140
3.75–36
7.5–72
6–45
4–36
3.3–30
5–47
VDD = 3.3 V
0 - 70
°C
3–18
15–100
3.75–25
7.5–50
6–34
4–26
3.3–20
5–27
-40 to +85
°C
3–16
15–90
3.75–22
7.5–45
6–30
4–23
3.3–18
5–24
ICS525-02 Output Frequency and Output Divider Table
S2
S1
S0 CLK Output
Pin 5 Pin 4 Pin 3
Divider
Output Frequency Range (MHz)
VDD = 5 V
-40 to +85
°C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
2
8
4
5
7
1
3
5–67
15–200
3.75–50
7.5–100
6–80
4–57
30–250
10–133
VDD = 3.3 V
-40 to +85
°C
5–40
15–120
3.75–30
7.5–60
6–48
4–34
30–200
10–80
ICS525-11 Output Frequency and Output Divider Table
S2
S1
S0 CLK Output
Pin 5 Pin 4 Pin 3
Divider
Output Frequency Range (MHz)
VDD = 5 V
0 - 70
°C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
2
8
4
5
7
9
6
0.75–6.5
3.75–40
0.94–10
1.875–20
1.5–12.5
1–10
0.83–8.33
1.25–13.25
-40 to +85
°C
0.75–5.75
3.75–35
0.94–9
1.875–18
1.5–11.25
1–9
0.83–7.5
1.25–11.75
VDD = 3.3 V
0 - 70
°C
0.75–4.5
3.75–25
0.94–6.25
1.875–12.5
1.5–8.5
1–6.5
0.83–5
1.25–6.75
-40 to +85
°C
0.75–4
3.75–22.5
0.94–5.5
1.875–11.25
1.5–7.5
1–5.75
0.83–4.5
1.25–6
MDS 525-01/02/11/12 Q
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
ICS525-01/02/11/12
User Configurable Clock
ICS525-12 Output Frequency and Output Divider Table
S2
S1
S0 CLK Output
Pin 5 Pin 4 Pin 3
Divider
Output Frequency Range (MHz)
VDD = 5 V
-40 to +85
°C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
2
8
4
5
7
1
3
1.25–16.75
3.75–50
0.94–12.5
1.875–25
1.5–20
1–14.25
7.5–62.5
2.5–33.25
VDD = 3.3 V
-40 to +85
°C
1.25–10
3.75–30
0.94–7.5
1.875–15
1.5–12
1–8.5
7.5–50
2.5–20
MDS 525-01/02/11/12 Q
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
ICS525-01/02/11/12
User Configurable Clock
(
VDW + 8
)
(
RDW + 2
) •
OD
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-01/02/11/12 requries two 0.01µF
decoupling capacitors to be connected between VDD
and GND, one on each side of the chip. The capacitor
must be connected close to the device to minimize lead
inductance.
-
CLK
Frequency = Input Frequency
×
2x
--------------------------------------------
Where:
Reference Divider Word (RDW) = 0 to 127 (0 not
permitted for ICS525-01/-11)
VCO Divider Word (VDW) = 0 to 511 (0, 1, 2, 3 not
permitted for ICS525-01/-11)
Output Divider (OD) = values on pages 3-4
Also, the following operating ranges should be
observed:
1. The output frequency must be in the ranges listed on
pages 3-4.
2. The phase detector frequency must be above 200
kHz.
InputFrequency
200kHz < ----------------------------------------------
-
(
RDW + 2
)
External Resistors
A 33Ω series termination resistor should be used on
the CLK and REF pins.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on
either).
Since all of the inputs have pull-up resistors, it is only
necessary to ground the pins that need to be set to
zero.
Which Part to Use?
The ICS525-01 is the original configurable clock.
The ICS525-02 has a higher maximum output
grequency and a slightly different set of output dividers.
The ICS525-11 has the same divider set as the -01 but
is optimized for low frequency operation.
The ICS525-12 has the same divider set as the -02 but
is optimized for low frequency operation.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site.
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the tables on pages
3-4. To replace a standard oscillator, users should
connect the divider select input pins directly to ground
(or VDD, although this is not required because of
internal pull-ups) during Printed Circuit Board layout.
The ICS525 will automatically produce the correct
frequency when all components are soldered. It is also
possible to connect the inputs to parallel I/O ports to
switch frequencies. By choosing divides carefully, the
number of inputs which need to be changed can be
minimized. Observe the restrictions on allowed values
of VDW and RDW.
Configuration Pin Settings
The output of the ICS525 can be determined by the
following simple equation:
MDS 525-01/02/11/12 Q
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
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