MC10124
Quad TTL to MECL
Translator
The MC10124 is a quad translator for interfacing data and control
signals between a saturated logic section and the MECL section of
digital systems. The MC10124 has TTL compatible inputs, and
MECL complementary open–emitter outputs that allow use as an
inverting/ non–inverting translator or as a differential line driver.
When the common strobe input is at the low logic level, it forces all
true outputs to a MECL low logic state and all inverting outputs to a
MECL high logic state.
Power supply requirements are ground, +5.0 Volts, and –5.2 Volts.
Propagation delay of the MC10124 is typically 3.5 ns. The dc levels
are standard or Schottky TTL in, MECL 10,000 out.
An advantage of this device is that TTL level information can be
transmitted differentially, via balanced twisted pair lines, to the MECL
equipment, where the signal can be received by the MC10115 or
MC10116 differential line receivers. The MC10124 is useful in
computers, instrumentation, peripheral controllers, test equipment,
and digital communications systems.
•
P
D
= 380 mW typ/pkg (No Load)
•
t
pd
= 3.5 ns typ (+ 1.5 Vdc in to 50% out)
•
t
r
, t
f
= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
5
6
7
10
11
Gnd
=
V
CC
(+5.0Vdc) =
V
EE
(-5.2Vdc) =
4
2
3
1
12
15
13
14
PIN 16
PIN 9
PIN 8
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
PDIP–16
P SUFFIX
CASE 648
1
1
PLCC–20
FN SUFFIX
CASE 775
10124
AWLYYWW
MC10124P
AWLYYWW
MC10124L
AWLYYWW
ORDERING INFORMATION
Device
MC10124L
MC10124P
Package
CDIP–16
PDIP–16
PLCC–20
Shipping
25 Units / Rail
25 Units / Rail
46 Units / Rail
DIP PIN ASSIGNMENT
B
OUT
A
OUT
B
OUT
A
OUT
A
IN
COMMON
STROBE
B
IN
MC10124FN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
C
OUT
D
OUT
D
OUT
C
OUT
D
IN
C
IN
V
CC
V
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
©
Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number:
MC10124/D
MC10124
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
Test
8
9
9
6
7
6
7
6
7
6
7
1
3
1
3
1
3
1
3
–1.060
–1.060
–1.890
–1.890
–1.080
–1.080
–1.655
–1.655
5.5
5.5
–1.5
–1.5
–0.890
–0.890
–1.675
–1.675
–0.960
–0.960
–1.850
–1.850
–0.980
–0.980
–1.630
–1.630
–30°C
Min
Max
72
16
25
200
50
–12.8
–3.2
5.5
5.5
–1.5
–1.5
–0.810
–0.810
–1.650
–1.650
–0.890
–0.890
–1.825
–1.825
–0.910
–0.910
–1.595
–1.595
Min
+25°C
Typ
Max
66
16
25
200
50
–12.8
–3.2
5.5
5.5
–1.5
–1.5
–0.700
–0.700
–1.615
–1.615
Min
+85°C
Max
72
18
25
200
50
–12.8
–3.2
Unit
mAdc
mAdc
mAdc
µAdc
mAdc
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
ns
t
6+1+
t
6–1–
t
7+1+
t
7–1–
t
7+3–
t
7–3+
t
1+
t
1–
1
1
1
1
3
3
1
1
1.5
1.0
1.5
1.0
1.5
1.0
1.0
1.0
6.8
6.0
6.8
6.0
6.8
6.0
4.2
4.2
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
3.5
3.5
3.5
3.5
3.5
3.5
2.5
2.5
6.0
6.0
6.0
6.0
6.0
6.0
3.9
3.9
1.0
1.5
1.0
1.5
1.0
1.5
1.1
1.1
6.0
6.8
6.0
6.8
6.0
6.8
4.3
4.3
Characteristic
Negative Power Supply
Drain Current
Positive Power Su y
os e o e Supply
Drain Current
Reverse Current
Forward Current
Input Breakdown Voltage
Clamp Input Voltage
High Output Voltage
Low Output Voltage
High Threshold Voltage
Low Threshold Voltage
Switching Times
Load)
(50Ω
Symbol
I
E
I
CCH
I
CCL
I
R
I
F
BV
in
V
I
V
OH
V
OL
V
OHA
V
OLA
Propagation Delay
(+3.5Vdc to 50%)
1
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
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2
MC10124
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
–30°C
+25°C
+85°C
Pin
Under
Test
8
9
9
6
7
6
7
6
7
6
7
1
3
1
3
1
3
1
3
6,7
6,7
6,7
6,7
6
6
6
6
+6.0 V
t
6+1+
t
6–1–
t
7+1+
t
7–1–
t
7+3–
t
7–3+
t
1+
t
1–
1
1
1
1
3
3
1
1
7
7
6
6
6
6
6
6
Pulse In
6
6
7
7
7
7
7
7
7
7
7
7
Pulse Out
1
1
1
1
3
3
1
1
5,7,10,11
6
5,7,10,11
6
6
7
5,6,7,10,11
V
IH
+4.0
+4.0
+4.0
V
ILmax
+0.40
+0.40
+0.40
V
IHA’
+2.00
+1.80
+1.80
V
ILA’
+1.10
+1.10
+0.90
V
F
+0.40
+0.40
+0.40
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IH
V
ILmax
V
IHA’
V
ILA’
V
F
Gnd
16
16
5,6,7,10,11,16
Characteristic
Negative Power Supply Drain
Current
Positive Power Su y Drain
os e o e Supply a
Current
Reverse Current
Forward Current
Input Breakdown Voltage
Clamp Input Voltage
High Output Voltage
Low Output Voltage
High Threshold Voltage
Low Threshold Voltage
Switching Times
(50Ω Load)
Symbol
I
E
I
CCH
I
CCL
I
R
I
F
BV
in
V
I
V
OH
V
OL
V
OHA
V
OLA
16
16
16
16
5,7,10,11,16
6,16
16
16
16
16
16
16
16
16
16
16
+2.0 V
16
16
16
16
16
16
16
16
Propagation Delay
(+3.5Vdc to 50%)
1
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
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3
MC10124
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
–30°C
+25°C
+85°C
Pin
Under
Test
8
9
9
6
7
6
7
6
7
6
7
1
3
1
3
1
3
1
3
6
7
V
R
+2.40
+2.40
+2.40
V
CC
+5.00
+5.00
+5.00
V
EE
–5.2
–5.2
–5.2
I
I
–10
–10
–10
(mA)
I
in
+1.0
+1.0
+1.0
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
R
V
CC
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
+7.0 V
V
EE
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
–3.2 V
8
8
8
8
8
8
8
8
6
7
6
7
I
I
I
in
Gnd
16
16
5,6,7,10,11,16
Characteristic
Negative Power Supply Drain
Current
Positive Power Su y Drain
os e o e Supply a
Current
Reverse Current
Forward Current
Input Breakdown Voltage
Clamp Input Voltage
High Output Voltage
Low Output Voltage
High Threshold Voltage
Low Threshold Voltage
Switching Times
(50Ω Load)
Symbol
I
E
I
CCH
I
CCL
I
R
I
F
BV
in
V
I
V
OH
V
OL
V
OHA
V
OLA
16
16
16
16
5,7,10,11,16
6,16
16
16
16
16
16
16
16
16
16
16
+2.0 V
16
16
16
16
16
16
16
16
Propagation Delay
(+3.5Vdc to 50%)
1
t
6+1+
t
6–1–
t
7+1+
t
7–1–
t
7+3–
t
7–3+
t
1+
t
1–
1
1
1
1
3
3
1
1
9
9
9
9
9
9
9
9
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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4
MC10124
SWITCHING TIME TEST CIRCUIT
V
out
NAND
+7.0 Vdc
0.1
µF
Coax
Coax
V
out
AND
V
in
+6.0 Vdc
V
CC
Coax
0.1
µF
25
µF
Input
Pulse Generator
5
6
7
10
11
4
2
3
1
12
15
13
14
16
8
0.1
µF
Unused outputs connected to a
50-ohm resistor to ground.
Input Pulse
t+ = t- = 5.5
±0.5
ns
(10 to 90%)
0.1
µF
50-ohm termination to ground lo-
cated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TP
in
to input pin and
TP
out
to output pin.
25
µF
+ 2.0 Vdc
V
EE
-3.2 Vdc
NOTE: All power supply and logic levels are shown
shifted 2 volts positive.
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5
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