GS8673ET36BGK-550 datasheet, PDF

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GS8673ET36BGK-550: DescriptionDDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260; Categorystorage storage; File Size449KB，34 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8673ET36BGK-550 Overview

DDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260

GS8673ET36BGK-550 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	GSI Technology
package instruction	HBGA,
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Factory Lead Time	12 weeks
Maximum access time	0.4 ns
Other features	IT ALSO OPERATES AT 1.35 V TYPICAL VOLTAGE
JESD-30 code	R-PBGA-B260
length	22 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	36
Number of functions	1
Number of terminals	260
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	HBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, HEAT SINK/SLUG
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum seat height	2.3 mm
Maximum supply voltage (Vsup)	1.4 V
Minimum supply voltage (Vsup)	1.25 V
Nominal supply voltage (Vsup)	1.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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GS8673ET18/36BK-675/625/550/500

260-Ball BGA

Commercial Temp

Industrial Temp

Features

• On-Chip ECC with virtually zero SER

• Configurable Read Latency (3.0 or 2.0 cycles)

• Simultaneous Read and Write SigmaDDR-IIIe™ Interface

• Common I/O Bus

• Double Data Rate interface

• Burst of 2 Read and Write

• Pipelined read operation

• Fully coherent Read and Write pipelines

• 1.35V nominal V

• 1.2V JESD8-16A BIC-3 Compliant Interface

• 1.5V HSTL Interface

• ZQ pin for programmable output drive impedance

• ZT for programmable input termination impedance

• Configurable Input Termination

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package

–K: 5/6 RoHS-compliant package

–GK: 6/6 RoHS-compliant package

72Mb SigmaDDR-IIIe™

Burst of 2 ECCRAM™

Clocking and Addressing Schemes

675 MHz–500 MHz

1.35V V

1.2V to 1.5V V

DDQ

The GS8673ET18/36BK SigmaDDR-IIIe ECCRAMs are

synchronous devices. They employ dual, single-ended master

clocks, CK and CK. These clocks are single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. CK and CK are used to control the address and control

input registers, as well as all output timing.

The KD and KD clocks are dual mesochronous (with respect to

CK and CK) input clocks that are used to control the data input

registers. Consequently, data input setup and hold windows

can be optimized independently of address and control input

setup and hold windows.

Each internal read and write operation in a SigmaDDR-IIIe B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaDDR-IIIe B2 ECCRAM is always one address

pin less than the advertised index depth (e.g. the 4M x 18 has

2M addressable index).

SigmaDDR-IIIe™ Family Overview

SigmaDDR-IIIe ECCRAMs are the Common I/O half of the

SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance

ECCRAMs. Although very similar to GSI's second generation

of networking SRAMs (the SigmaQuad-II/SigmaDDR-II

family), these third generation devices offer several new

features that help enable significantly higher performance.

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles, etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

Parameter Synopsis

Speed Bin

-675

-625

-550

-500

Operating Frequency

675 / 450 MHz

625 / 400 MHz

550 / 375 MHz

500 / 333 MHz

Data Rate (per pin)

1350 / 900 Mbps

1250 / 800 Mbps

1100 / 750 Mbps

1000 / 666 Mbps

Read Latency

3.0 / 2.0

1.3V to 1.4V

1.25V to 1.4V

Rev: 1.06 5/2012

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8673ET36BGK-550 Related Products

	GS8673ET36BGK-550	GS8673ET36BGK-500I	GS8673ET36BGK-500	GS8673ET36BGK-675	GS8673ET36BGK-675I	GS8673ET36BGK-550I	GS8673ET36BGK-625	GS8673ET36BGK-625I
Description	DDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260	DDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260	DDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260	DDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260	DDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260	DDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260	DDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260	DDR SRAM, 2MX36, 0.4ns, CMOS, PBGA260, BGA-260
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology	GSI Technology
package instruction	HBGA,	HBGA,	HBGA,	HBGA,	HBGA,	HBGA,	HBGA,	HBGA,
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
Factory Lead Time	12 weeks	12 weeks	12 weeks	12 weeks	12 weeks	12 weeks	12 weeks	12 weeks
Maximum access time	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns
JESD-30 code	R-PBGA-B260	R-PBGA-B260	R-PBGA-B260	R-PBGA-B260	R-PBGA-B260	R-PBGA-B260	R-PBGA-B260	R-PBGA-B260
length	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm
memory density	75497472 bit	75497472 bit	75497472 bit	75497472 bit	75497472 bit	75497472 bit	75497472 bit	75497472 bit
Memory IC Type	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
memory width	36	36	36	36	36	36	36	36
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	260	260	260	260	260	260	260	260
word count	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words	2097152 words
character code	2000000	2000000	2000000	2000000	2000000	2000000	2000000	2000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
organize	2MX36	2MX36	2MX36	2MX36	2MX36	2MX36	2MX36	2MX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HBGA	HBGA	HBGA	HBGA	HBGA	HBGA	HBGA	HBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Maximum seat height	2.3 mm	2.3 mm	2.3 mm	2.3 mm	2.3 mm	2.3 mm	2.3 mm	2.3 mm
Maximum supply voltage (Vsup)	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V	1.4 V
Minimum supply voltage (Vsup)	1.25 V	1.25 V	1.25 V	1.3 V	1.3 V	1.25 V	1.3 V	1.3 V
Nominal supply voltage (Vsup)	1.3 V	1.3 V	1.3 V	1.35 V	1.35 V	1.3 V	1.35 V	1.35 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Base Number Matches	1	1	1	1	1	1	1	1

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