XC9536XV-7PC44I datasheet, PDF

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XC9536XV-7PC44I: DescriptionEE PLD, 7.5 ns, PQFP44; CategoryProgrammable logic devices Programmable logic; File Size66KB，8 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC9536XV-7PC44I Overview

EE PLD, 7.5 ns, PQFP44

XC9536XV-7PC44I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	LCC
package instruction	PLASTIC, LCC-44
Contacts	44
Reach Compliance Code	_compli
ECCN code	EAR99
Other features	YES
In-system programmable	YES
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
JTAG BST	YES
length	16.5862 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	34
Number of macro cells	36
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	0 DEDICATED INPUTS, 34 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	1.8/3.3,2.5 V
Programmable logic type	FLASH PLD
propagation delay	7.5 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	2.62 V
Minimum supply voltage	2.37 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	16.5862 mm
Base Number Matches	1

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XC9536XV High-performance

CPLD

DS053 (v2.6) April 15, 2005

Product Specification

For a general estimate of I

, the following equation may be

used:

TOTAL

= P

INT

+ P

= I

CCINT

x V

CCINT

+ P

Separating internal and I/O power here is convenient

because XC9500XV CPLDs also separate the correspond-

ing power pins. P

is a strong function of the load capaci-

tance driven, so it is handled by I = CVf. I

CCINT

is another

situation that reflects the actual design considered and the

internal switching speeds. An estimation expression for

CCINT

(taken from simulation) is:

CCINT

(mA) = MC

(0.122 X PT

+ 0.238) + MC

(0.042 x

+ 0.171) + 0.04(MC

+ MC

) x f

MAX

x MC

TOG

where:

= # macrocells used in high speed mode

= #macrocells used in low power mode

= average p-terms used per high speed macrocell

= average p-terms used over low power macrocell

MAX

= max clocking frequency in the device

TOG

= % macrocells toggling on each clock (12% is

frequently a good estimate

This calculation was derived from laboratory measurements

of an XC9500XV part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual I

value varies with the design application and should be veri-

fied during normal system operation.

Figure 1

shows the

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

application note

XAPP361, “Planning for High Speed

XC9500XV Designs.”

Typical I

(mA)

200 MHz

Features

•

36 macrocells with 800 usable gates

Available in small footprint packages

- 44-pin PLCC (34 user I/O pins)

- 44-pin VQFP (34 user I/O pins)

- 48-pin CSP (36 user I/O pins)

Optimized for high-performance 2.5V systems

- Low power operation

- Multi-voltage operation

Advanced system features

- In-system programmable

- Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with

individual product-term allocation

- Local clock inversion with three global and one

product-term clocks

- Individual output enable per output pin

- Input hysteresis on all user and boundary-scan pin

inputs

- Bus-hold circuitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

- 20 year data retention

- ESD protection exceeding 2,000V

Pin-compatible with 3.3V-core XC9536XL device in the

44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages

•

Description

The XC9536XV is a 2.5V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of two

54V18 Function Blocks, providing 800 usable gates with

propagation delays of 5 ns. See

Figure 2

for architecture

overview.

H ig

for

P er

n ce

120 MHz

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XV device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

Low

100

150

Clock Frequency (MHz)

200

DS053_01_121501

Figure 1:

Typical I

vs. Frequency for XC9536XV

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS053 (v2.6) April 15, 2005

Product Specification

www.xilinx.com

XC9536XV-7PC44I Related Products

	XC9536XV-7PC44I	XC9536XV-7VQ44C	XC9536XV-7VQ44I	XC9536XV-5VQ44C	XC9536XV-7PC44C	XC9536XV-5CS48C	XC9536XV-7CS48I	XC9536XV	XC9536XV-7CS48C	XC9536XV-5PC44C
Description	EE PLD, 7.5 ns, PQFP44	EE PLD, 7.5 ns, PQFP44	EE PLD, 7.5 ns, PQFP44	EE PLD, 7.5 ns, PQFP44	EE PLD, 7.5 ns, PQFP44	EE PLD, 5 ns, PBGA48	EE PLD, 7.5 ns, PQFP44	EE PLD, 7.5 ns, PQFP44	EE PLD, 7.5 ns, PQFP44	EE PLD, 5 ns, PQCC44
Number of terminals	44	44	44	44	44	48	48	44	48	44
Maximum operating temperature	85 °C	70 °C	85 °C	70 °C	70 °C	70 °C	85 °C	70 Cel	70 °C	70 °C
organize	0 DEDICATED INPUTS, 34 I/O	0 DEDICATED INPUTS, 34 I/O	0 DEDICATED INPUTS, 34 I/O	0 DEDICATED INPUTS, 34 I/O	0 DEDICATED INPUTS, 34 I/O	0 DEDICATED INPUTS, 36 I/O	0 DEDICATED INPUTS, 36 I/O	0 DEDICATED INPUTS, 34 I/O	0 DEDICATED INPUTS, 36 I/O	0 DEDICATED INPUTS, 34 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Programmable logic type	FLASH PLD	FLASH PLD	FLASH PLD	FLASH PLD	FLASH PLD	FLASH PLD	FLASH PLD	electronic programmable logic devices	FLASH PLD	FLASH PLD
surface mount	YES	YES	YES	YES	YES	YES	YES	Yes	YES	YES
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	J BEND	GULL WING	GULL WING	GULL WING	J BEND	BALL	BALL	GULL WING	BALL	J BEND
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	BOTTOM	BOTTOM	Four	BOTTOM	QUAD
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	-	incompatible	incompatible
Maker	XILINX	XILINX	XILINX	XILINX	XILINX	-	XILINX	-	XILINX	XILINX
Parts packaging code	LCC	QFP	QFP	QFP	LCC	BGA	BGA	-	BGA	LCC
package instruction	PLASTIC, LCC-44	TQFP, TQFP44,.47SQ,32	TQFP, TQFP44,.47SQ,32	TQFP, TQFP44,.47SQ,32	PLASTIC, LCC-44	CSP-48	CSP-48	-	CSP-48	PLASTIC, LCC-44
Contacts	44	44	44	44	44	48	48	-	48	44
Reach Compliance Code	_compli	_compli	_compli	_compli	_compli	_compli	_compli	-	_compli	_compli
ECCN code	EAR99	-	-	EAR99	EAR99	EAR99	EAR99	-	EAR99	EAR99
Other features	YES	YES	YES	YES	YES	YES	YES	-	YES	YES
In-system programmable	YES	YES	YES	YES	YES	YES	YES	-	YES	YES
JESD-30 code	S-PQCC-J44	S-PQFP-G44	S-PQFP-G44	S-PQFP-G44	S-PQCC-J44	S-PBGA-B48	S-PBGA-B48	-	S-PBGA-B48	S-PQCC-J44
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	-	e0	e0
JTAG BST	YES	YES	YES	YES	YES	YES	YES	-	YES	YES
length	16.5862 mm	10 mm	10 mm	10 mm	16.5862 mm	7 mm	7 mm	-	7 mm	16.5862 mm
Humidity sensitivity level	3	3	3	3	3	3	3	-	3	3
Number of I/O lines	34	34	34	34	34	36	36	-	36	34
Number of macro cells	36	36	36	36	36	36	36	-	36	36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	TQFP	TQFP	TQFP	QCCJ	FBGA	FBGA	-	FBGA	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ	TQFP44,.47SQ,32	TQFP44,.47SQ,32	TQFP44,.47SQ,32	LDCC44,.7SQ	BGA48,7X7,32	BGA48,7X7,32	-	BGA48,7X7,32	LDCC44,.7SQ
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	-	SQUARE	SQUARE
Package form	CHIP CARRIER	FLATPACK, THIN PROFILE	FLATPACK, THIN PROFILE	FLATPACK, THIN PROFILE	CHIP CARRIER	GRID ARRAY, FINE PITCH	GRID ARRAY, FINE PITCH	-	GRID ARRAY, FINE PITCH	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225	225	225	225	225	240	240	-	240	225
power supply	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	1.8/3.3,2.5 V	-	1.8/3.3,2.5 V	1.8/3.3,2.5 V
propagation delay	7.5 ns	7.5 ns	7.5 ns	5 ns	7.5 ns	5 ns	7.5 ns	-	7.5 ns	5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	1.2 mm	1.2 mm	1.2 mm	4.57 mm	1.8 mm	1.8 mm	-	1.8 mm	4.57 mm
Maximum supply voltage	2.62 V	2.62 V	2.62 V	2.62 V	2.62 V	2.62 V	2.62 V	-	2.62 V	2.62 V
Minimum supply voltage	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	-	2.37 V	2.37 V
Nominal supply voltage	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	-	2.5 V	2.5 V
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	-	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn85Pb15)
Terminal pitch	1.27 mm	0.8 mm	0.8 mm	0.8 mm	1.27 mm	0.8 mm	0.8 mm	-	0.8 mm	1.27 mm
Maximum time at peak reflow temperature	30	30	30	30	30	30	30	-	30	30
width	16.5862 mm	10 mm	10 mm	10 mm	16.5862 mm	7 mm	7 mm	-	7 mm	16.5862 mm

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