0
R
XC9536XV High-performance
CPLD
0
1
DS053 (v2.6) April 15, 2005
Product Specification
For a general estimate of I
CC
, the following equation may be
used:
P
TOTAL
= P
INT
+ P
IO
= I
CCINT
x V
CCINT
+ P
IO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. P
IO
is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. I
CCINT
is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
I
CCINT
(taken from simulation) is:
I
CCINT
(mA) = MC
HS
(0.122 X PT
HS
+ 0.238) + MC
LP
(0.042 x
PT
LP
+ 0.171) + 0.04(MC
HS
+ MC
LP
) x f
MAX
x MC
TOG
where:
MC
HS
= # macrocells used in high speed mode
MC
LP
= #macrocells used in low power mode
PT
HS
= average p-terms used per high speed macrocell
PT
LP
= average p-terms used over low power macrocell
f
MAX
= max clocking frequency in the device
MC
TOG
= % macrocells toggling on each clock (12% is
frequently a good estimate
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation.
Figure 1
shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note
XAPP361, “Planning for High Speed
XC9500XV Designs.”
60
50
Typical I
CC
(mA)
200 MHz
Features
•
•
36 macrocells with 800 usable gates
Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (36 user I/O pins)
Optimized for high-performance 2.5V systems
- Low power operation
- Multi-voltage operation
Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- 20 year data retention
- ESD protection exceeding 2,000V
Pin-compatible with 3.3V-core XC9536XL device in the
44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages
•
•
•
•
•
•
•
Description
The XC9536XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of two
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See
Figure 2
for architecture
overview.
40
H ig
h
for
P er
ma
n ce
120 MHz
er
30
20
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
P
Low
ow
10
0
50
100
150
Clock Frequency (MHz)
200
DS053_01_121501
Figure 1:
Typical I
CC
vs. Frequency for XC9536XV
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS053 (v2.6) April 15, 2005
Product Specification
www.xilinx.com
1
XC9536XV High-performance CPLD
R
3
JTAG Port
1
JTAG
Controller
In-System Programming Controller
54
I/O
I/O
I/O
Fast CONNECT II Switch Matrix
I/O
54
18
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
3
I/O/GCK
1
I/O/GSR
I/O/GTS
2
DS053_02_041200
Figure 2:
XC9536XV Architecture
Function block outputs (indicated by the bold line) drive the I/O Blocks directly.
Supported I/O Standards
Table 1:
IOSTANDARD Options
IOSTANDARD
LVTTL
LVCMOS2
X25TO18
V
CCIO
3.3V
2.5V
1.8V
The LVTTL I/O standard is a general purpose EIA/JEDEC
standard for 3.3V applications that use an LVTTL input
buffer and Push-Pull output buffer. The LVCMOS2 standard
is used in 2.5V applications.
XC9500XV CPLDs are also 1.8V I/O compatible. The
X25TO18 setting is provided for generating 1.8V compatible
outputs from a CPLD normally operating in a 2.5V environ-
ment. The default I/O Standard for pads without IOSTAN-
DARD attributes is LVTTL for XC9500XV devices.
The XC9536XV CPLD features both LVCMOS and LVTTL
I/O implementations. See
Table 1
for I/O standard voltages.
2
www.xilinx.com
DS053 (v2.6) April 15, 2005
Product Specification
R
XC9536XV High-performance CPLD
Absolute Maximum Ratings
Symbol
V
CC
V
CCIO
V
IN
V
TS
T
STG
T
J
Description
Supply voltage relative to GND
Supply voltage for output drivers
Input voltage relative to GND
(1)
Voltage applied to 3-state output
(1)
Storage temperature (ambient)
Junction temperature
Value
–0.5 to 2.7
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 3.6
–65 to +150
+150
Units
V
V
V
V
o
C
o
C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For solder specifications, see
Xilinx Packaging.
Recommended Operation Conditions
Symbol
V
CCINT
V
CCIO
Parameter
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0
o
C to +70
o
C
Industrial T
A
= –40
o
C to +85
o
C
Min
2.37
2.37
3.0
2.37
1.71
0
1.7
0
Max
2.62
2.62
3.6
2.62
1.89
0.8
3.6
V
CCIO
V
V
V
V
V
V
Units
V
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Supply voltage for output drivers for 1.8V operation
V
IL
V
IH
V
O
Low-level input voltage
High-level input voltage
Output voltage
Quality and Reliability Characteristics
Symbol
T
DR
N
PE
V
ESD
Data Retention
Program/Erase Cycles (Endurance)
Electrostatic Discharge (ESD)
Parameter
Min
20
1,000
2,000
Max
-
-
-
Units
Years
Cycles
Volts
DS053 (v2.6) April 15, 2005
Product Specification
www.xilinx.com
3
XC9536XV High-performance CPLD
R
DC Characteristics
(Over Recommended Operating Conditions)
Symbol
V
OH
Parameter
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output high voltage for 1.8V outputs
V
OL
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Output low voltage for 1.8V outputs
I
IL
Input leakage current
Test Conditions
I
OH
= –4.0 mA
I
OH
= –1.0 mA
I
OH
= –100
µA
I
OL
= 8.0 mA
I
OL
= 1.0 mA
I
OL
= 100
µA
V
CC
= 2.62V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
V
CC
= 2.62V
V
CCIO
= 3.6V
V
IN
= GND or 3.6V
V
CC
min < V
IN
< 3.6V
C
IN
I
CC
I/O capacitance
Operating Supply Current
(low power mode, active)
V
IN
= GND
f = 1.0 MHz
V
I
= GND, No load
f = 1.0 MHz
Min
2.4
2.0
90% V
CCIO
-
-
-
-
Max
-
-
-
0.4
0.4
0.4
±10
Units
V
V
V
V
V
V
µA
I
IH
Input high-Z leakage current
-
±10
µA
-
-
7
±150
10
µA
pF
mA
AC Characteristics
XC9536XV-5
Symbol
T
PD
T
SU
T
H
T
CO
f
SYSTEM
T
PSU
T
PH
T
PCO
T
OE
T
OD
T
POE
T
POD
T
AO
T
PAO
T
WLH
T
PLH
T
APRPW
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
P-term S/R to output valid
GCK pulse width (High or Low)
P-term clock pulse width (High or Low)
Asynchronous preset/reset pulse width (High or Low)
Parameter
Min
-
3.5
0
-
-
1.0
2.5
-
-
-
-
-
-
-
2.2
5.0
5.0
Max
5.0
-
-
3.5
222.2
-
-
6.0
4.0
4.0
7.0
7.0
10.0
10.7
-
-
-
XC9536XV-7
Min
-
4.8
0
-
-
1.6
3.2
-
-
-
-
-
-
-
4.0
6.5
6.5
Max
7.5
-
-
4.5
125.0
-
-
7.7
5.0
5.0
9.5
9.5
12.0
12.6
-
-
-
Units
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
www.xilinx.com
DS053 (v2.6) April 15, 2005
Product Specification
R
XC9536XV High-performance CPLD
V
TEST
R
1
Device Output
R
2
C
L
Output Type
V
CCIO
3.3V
2.5V
1.8V
V
TEST
3.3V
2.5V
1.8V
R
1
320Ω
250Ω
10KΩ
R
2
360Ω
660Ω
14KΩ
C
L
35 pF
35 pF
35 pF
DS051_03_0601000
Figure 3:
AC Load Circuit
Internal Timing Parameters
XC9536XV-5
Symbol
Buffer Delays
T
IN
T
GCK
T
GSR
T
GTS
T
OUT
T
EN
T
PTCK
T
PTSR
T
PTTS
T
PDI
T
SUI
T
HI
T
ECSU
T
ECHO
T
COI
T
AOI
T
RAI
T
LOGI
T
LOGILP
T
F
T
PTA
T
PTA2
T
SLEW
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
Product term clock delay
Product term set/reset delay
Product term 3-state delay
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
Internal low power logic delay
Fast CONNECT II feedback delay
Incremental product term allocator delay
Adjacent macrocell p-term allocator delay
Slew-rate limited delay
-
-
-
-
-
-
-
-
-
-
2.0
1.5
2.0
1.5
-
-
5.0
-
-
-
-
-
-
0.7
5.7
1.6
0.7
0.3
3.0
2.0
1.2
2.0
4.0
2.1
0
1.7
0.7
5.0
0.2
-
-
-
-
0.2
5.9
-
-
-
-
-
-
-
-
-
-
2.6
2.2
2.6
2.2
-
-
7.5
-
-
-
-
-
-
1.4
6.4
3.5
0.8
0.3
4.0
2.3
1.5
3.1
5.0
2.5
0
2.4
1.4
7.2
1.3
-
-
-
-
0.5
6.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min
Max
XC9536XV-7
Min
Max
Units
Product Term Control Delays
Internal Register and Combinatorial Delays
Feedback Delays
Time Adders
DS053 (v2.6) April 15, 2005
Product Specification
www.xilinx.com
5
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