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XC9536XV

Description
EE PLD, 7.5 ns, PQFP44
Categorysemiconductor    Programmable logic devices   
File Size66KB,8 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
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XC9536XV Overview

EE PLD, 7.5 ns, PQFP44

XC9536XV Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals44
Maximum operating temperature70 Cel
Minimum operating temperature0.0 Cel
Maximum supply/operating voltage2.62 V
Minimum supply/operating voltage2.37 V
Rated supply voltage2.5 V
Number of input and output buses34
Processing package descriptionVQFP-44
stateDISCONTINUED
packaging shapeSQUARE
Package SizeFLATPACK, THIN PROFILE
surface mountYes
Terminal formGULL WING
Terminal spacing0.8000 mm
terminal coatingtin lead
Terminal locationFour
Packaging MaterialsPlastic/Epoxy
Temperature levelCOMMERCIAL
organize0 DEDICATED INPUTS, 34 I/O
Maximum FCLK clock frequency125 MHz
Output functionMACROCELL
Programmable logic typeelectronic programmable logic devices
propagation delay TPD7.5 ns
Dedicated input quantity0.0
0
R
XC9536XV High-performance
CPLD
0
1
DS053 (v2.6) April 15, 2005
Product Specification
For a general estimate of I
CC
, the following equation may be
used:
P
TOTAL
= P
INT
+ P
IO
= I
CCINT
x V
CCINT
+ P
IO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. P
IO
is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. I
CCINT
is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
I
CCINT
(taken from simulation) is:
I
CCINT
(mA) = MC
HS
(0.122 X PT
HS
+ 0.238) + MC
LP
(0.042 x
PT
LP
+ 0.171) + 0.04(MC
HS
+ MC
LP
) x f
MAX
x MC
TOG
where:
MC
HS
= # macrocells used in high speed mode
MC
LP
= #macrocells used in low power mode
PT
HS
= average p-terms used per high speed macrocell
PT
LP
= average p-terms used over low power macrocell
f
MAX
= max clocking frequency in the device
MC
TOG
= % macrocells toggling on each clock (12% is
frequently a good estimate
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation.
Figure 1
shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note
XAPP361, “Planning for High Speed
XC9500XV Designs.”
60
50
Typical I
CC
(mA)
200 MHz
Features
36 macrocells with 800 usable gates
Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (36 user I/O pins)
Optimized for high-performance 2.5V systems
- Low power operation
- Multi-voltage operation
Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- 20 year data retention
- ESD protection exceeding 2,000V
Pin-compatible with 3.3V-core XC9536XL device in the
44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages
Description
The XC9536XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of two
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See
Figure 2
for architecture
overview.
40
H ig
h
for
P er
ma
n ce
120 MHz
er
30
20
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
P
Low
ow
10
0
50
100
150
Clock Frequency (MHz)
200
DS053_01_121501
Figure 1:
Typical I
CC
vs. Frequency for XC9536XV
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS053 (v2.6) April 15, 2005
Product Specification
www.xilinx.com
1

XC9536XV Related Products

XC9536XV XC9536XV-7VQ44C XC9536XV-7VQ44I XC9536XV-7PC44I XC9536XV-5VQ44C XC9536XV-7PC44C XC9536XV-5CS48C XC9536XV-7CS48I XC9536XV-7CS48C XC9536XV-5PC44C
Description EE PLD, 7.5 ns, PQFP44 EE PLD, 7.5 ns, PQFP44 EE PLD, 7.5 ns, PQFP44 EE PLD, 7.5 ns, PQFP44 EE PLD, 7.5 ns, PQFP44 EE PLD, 7.5 ns, PQFP44 EE PLD, 5 ns, PBGA48 EE PLD, 7.5 ns, PQFP44 EE PLD, 7.5 ns, PQFP44 EE PLD, 5 ns, PQCC44
Number of terminals 44 44 44 44 44 44 48 48 48 44
Maximum operating temperature 70 Cel 70 °C 85 °C 85 °C 70 °C 70 °C 70 °C 85 °C 70 °C 70 °C
surface mount Yes YES YES YES YES YES YES YES YES YES
Terminal form GULL WING GULL WING GULL WING J BEND GULL WING J BEND BALL BALL BALL J BEND
Terminal location Four QUAD QUAD QUAD QUAD QUAD BOTTOM BOTTOM BOTTOM QUAD
Temperature level COMMERCIAL COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL COMMERCIAL
organize 0 DEDICATED INPUTS, 34 I/O 0 DEDICATED INPUTS, 34 I/O 0 DEDICATED INPUTS, 34 I/O 0 DEDICATED INPUTS, 34 I/O 0 DEDICATED INPUTS, 34 I/O 0 DEDICATED INPUTS, 34 I/O 0 DEDICATED INPUTS, 36 I/O 0 DEDICATED INPUTS, 36 I/O 0 DEDICATED INPUTS, 36 I/O 0 DEDICATED INPUTS, 34 I/O
Output function MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
Programmable logic type electronic programmable logic devices FLASH PLD FLASH PLD FLASH PLD FLASH PLD FLASH PLD FLASH PLD FLASH PLD FLASH PLD FLASH PLD
Is it Rohs certified? - incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible
Maker - XILINX XILINX XILINX XILINX XILINX - XILINX XILINX XILINX
Parts packaging code - QFP QFP LCC QFP LCC BGA BGA BGA LCC
package instruction - TQFP, TQFP44,.47SQ,32 TQFP, TQFP44,.47SQ,32 PLASTIC, LCC-44 TQFP, TQFP44,.47SQ,32 PLASTIC, LCC-44 CSP-48 CSP-48 CSP-48 PLASTIC, LCC-44
Contacts - 44 44 44 44 44 48 48 48 44
Reach Compliance Code - _compli _compli _compli _compli _compli _compli _compli _compli _compli
Other features - YES YES YES YES YES YES YES YES YES
In-system programmable - YES YES YES YES YES YES YES YES YES
JESD-30 code - S-PQFP-G44 S-PQFP-G44 S-PQCC-J44 S-PQFP-G44 S-PQCC-J44 S-PBGA-B48 S-PBGA-B48 S-PBGA-B48 S-PQCC-J44
JESD-609 code - e0 e0 e0 e0 e0 e0 e0 e0 e0
JTAG BST - YES YES YES YES YES YES YES YES YES
length - 10 mm 10 mm 16.5862 mm 10 mm 16.5862 mm 7 mm 7 mm 7 mm 16.5862 mm
Humidity sensitivity level - 3 3 3 3 3 3 3 3 3
Number of I/O lines - 34 34 34 34 34 36 36 36 34
Number of macro cells - 36 36 36 36 36 36 36 36 36
Package body material - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - TQFP TQFP QCCJ TQFP QCCJ FBGA FBGA FBGA QCCJ
Encapsulate equivalent code - TQFP44,.47SQ,32 TQFP44,.47SQ,32 LDCC44,.7SQ TQFP44,.47SQ,32 LDCC44,.7SQ BGA48,7X7,32 BGA48,7X7,32 BGA48,7X7,32 LDCC44,.7SQ
Package shape - SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
Package form - FLATPACK, THIN PROFILE FLATPACK, THIN PROFILE CHIP CARRIER FLATPACK, THIN PROFILE CHIP CARRIER GRID ARRAY, FINE PITCH GRID ARRAY, FINE PITCH GRID ARRAY, FINE PITCH CHIP CARRIER
Peak Reflow Temperature (Celsius) - 225 225 225 225 225 240 240 240 225
power supply - 1.8/3.3,2.5 V 1.8/3.3,2.5 V 1.8/3.3,2.5 V 1.8/3.3,2.5 V 1.8/3.3,2.5 V 1.8/3.3,2.5 V 1.8/3.3,2.5 V 1.8/3.3,2.5 V 1.8/3.3,2.5 V
propagation delay - 7.5 ns 7.5 ns 7.5 ns 5 ns 7.5 ns 5 ns 7.5 ns 7.5 ns 5 ns
Certification status - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height - 1.2 mm 1.2 mm 4.57 mm 1.2 mm 4.57 mm 1.8 mm 1.8 mm 1.8 mm 4.57 mm
Maximum supply voltage - 2.62 V 2.62 V 2.62 V 2.62 V 2.62 V 2.62 V 2.62 V 2.62 V 2.62 V
Minimum supply voltage - 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V 2.37 V
Nominal supply voltage - 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
technology - CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Terminal surface - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn85Pb15) Tin/Lead (Sn/Pb) Tin/Lead (Sn85Pb15) Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Tin/Lead (Sn85Pb15)
Terminal pitch - 0.8 mm 0.8 mm 1.27 mm 0.8 mm 1.27 mm 0.8 mm 0.8 mm 0.8 mm 1.27 mm
Maximum time at peak reflow temperature - 30 30 30 30 30 30 30 30 30
width - 10 mm 10 mm 16.5862 mm 10 mm 16.5862 mm 7 mm 7 mm 7 mm 16.5862 mm
ECCN code - - - EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
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