CDCV857AGQLR datasheet, PDF - EEWORLD Datasheet

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CDCV857AGQLR: DescriptionClock Drivers & Distribution 2.5V Clock; Categorylogic logic; File Size379KB，16 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Related ProductsFound20parts with similar functions to CDCV857AGQLR

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CDCV857AGQLR Overview

Clock Drivers & Distribution 2.5V Clock

CDCV857AGQLR Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Texas Instruments
Parts packaging code	BGA
package instruction	VFBGA, BGA56,6X10,25
Contacts	56
Reach Compliance Code	_compli
Factory Lead Time	1 week
series	857
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PBGA-B56
JESD-609 code	e0
length	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.012 A
Humidity sensitivity level	2A
Number of functions	1
Number of inverted outputs
Number of terminals	56
Actual output times	10
Maximum operating temperature	85 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA56,6X10,25
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	220
power supply	2.5 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.65 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.5 mm
minfmax	180 MHz

CDCV857AGQLR Related Products

	CDCV857AGQLR	CDCV857ADGG	CDCV857ADGGR	CDCV857ADGGG4	CDCV857ADGGRG4
Description	Clock Drivers & Distribution 2.5V Clock	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85	2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85
Brand Name	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
Is it lead-free?	Contains lead	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	incompatible	conform to	conform to	conform to	conform to
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
Parts packaging code	BGA	TSSOP	TSSOP	TSSOP	TSSOP
package instruction	VFBGA, BGA56,6X10,25	TSSOP, TSSOP48,.3,20	TSSOP, TSSOP48,.3,20	TSSOP, TSSOP48,.3,20	TSSOP, TSSOP48,.3,20
Contacts	56	48	48	48	48
Reach Compliance Code	_compli	compli	compli	compli	compli
Factory Lead Time	1 week	1 week	1 week	1 week	6 weeks
series	857	857	857	857	857
Input adjustment	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL
JESD-30 code	R-PBGA-B56	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48
JESD-609 code	e0	e4	e4	e4	e4
length	7 mm	12.5 mm	12.5 mm	12.5 mm	12.5 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.012 A	0.012 A	0.012 A	0.012 A	0.012 A
Humidity sensitivity level	2A	2	2	2	2
Number of functions	1	1	1	1	1
Number of terminals	56	48	48	48	48
Actual output times	10	10	10	10	10
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VFBGA	TSSOP	TSSOP	TSSOP	TSSOP
Encapsulate equivalent code	BGA56,6X10,25	TSSOP48,.3,20	TSSOP48,.3,20	TSSOP48,.3,20	TSSOP48,.3,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	220	260	260	260	260
power supply	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.075 ns	0.075 ns	0.075 ns	0.075 ns	0.075 ns
Maximum seat height	1 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal surface	Tin/Lead (Sn/Pb)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	BALL	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	BOTTOM	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	4.5 mm	6.1 mm	6.1 mm	6.1 mm	6.1 mm
minfmax	180 MHz	180 MHz	180 MHz	180 MHz	180 MHz
Load capacitance (CL)	-	14 pF	14 pF	14 pF	14 pF
method of packing	-	TUBE	TR	TUBE	TR
Maximum supply current (ICC)	-	12 mA	12 mA	12 mA	12 mA

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