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CDCV857ADGGG4

Description
2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85
Categorylogic    logic   
File Size379KB,16 Pages
ManufacturerTexas Instruments
Websitehttp://www.ti.com.cn/
Environmental Compliance
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CDCV857ADGGG4 Overview

2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85

CDCV857ADGGG4 Parametric

Parameter NameAttribute value
Brand NameTexas Instruments
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerTexas Instruments
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP48,.3,20
Contacts48
Reach Compliance Codecompli
Factory Lead Time1 week
series857
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G48
JESD-609 codee4
length12.5 mm
Load capacitance (CL)14 pF
Logic integrated circuit typePLL BASED CLOCK DRIVER
MaximumI(ol)0.012 A
Humidity sensitivity level2
Number of functions1
Number of inverted outputs
Number of terminals48
Actual output times10
Maximum operating temperature85 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP48,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTUBE
Peak Reflow Temperature (Celsius)260
power supply2.5 V
Maximum supply current (ICC)12 mA
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.075 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelOTHER
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width6.1 mm
minfmax180 MHz

CDCV857ADGGG4 Related Products

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Description 2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85 Clock Drivers & Distribution 2.5V Clock 2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications 48-TSSOP 0 to 85
Brand Name Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments
Is it lead-free? Lead free Lead free Lead free Contains lead Lead free
Is it Rohs certified? conform to conform to conform to incompatible conform to
Maker Texas Instruments Texas Instruments Texas Instruments Texas Instruments Texas Instruments
Parts packaging code TSSOP TSSOP TSSOP BGA TSSOP
package instruction TSSOP, TSSOP48,.3,20 TSSOP, TSSOP48,.3,20 TSSOP, TSSOP48,.3,20 VFBGA, BGA56,6X10,25 TSSOP, TSSOP48,.3,20
Contacts 48 48 48 56 48
Reach Compliance Code compli compli compli _compli compli
Factory Lead Time 1 week 1 week 1 week 1 week 6 weeks
series 857 857 857 857 857
Input adjustment DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL
JESD-30 code R-PDSO-G48 R-PDSO-G48 R-PDSO-G48 R-PBGA-B56 R-PDSO-G48
JESD-609 code e4 e4 e4 e0 e4
length 12.5 mm 12.5 mm 12.5 mm 7 mm 12.5 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
MaximumI(ol) 0.012 A 0.012 A 0.012 A 0.012 A 0.012 A
Humidity sensitivity level 2 2 2 2A 2
Number of functions 1 1 1 1 1
Number of terminals 48 48 48 56 48
Actual output times 10 10 10 10 10
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP TSSOP VFBGA TSSOP
Encapsulate equivalent code TSSOP48,.3,20 TSSOP48,.3,20 TSSOP48,.3,20 BGA56,6X10,25 TSSOP48,.3,20
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH GRID ARRAY, VERY THIN PROFILE, FINE PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260 220 260
power supply 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.075 ns 0.075 ns 0.075 ns 0.075 ns 0.075 ns
Maximum seat height 1.2 mm 1.2 mm 1.2 mm 1 mm 1.2 mm
Maximum supply voltage (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
Minimum supply voltage (Vsup) 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V
Nominal supply voltage (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V
surface mount YES YES YES YES YES
Temperature level OTHER OTHER OTHER OTHER OTHER
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Tin/Lead (Sn/Pb) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form GULL WING GULL WING GULL WING BALL GULL WING
Terminal pitch 0.5 mm 0.5 mm 0.5 mm 0.65 mm 0.5 mm
Terminal location DUAL DUAL DUAL BOTTOM DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 6.1 mm 6.1 mm 6.1 mm 4.5 mm 6.1 mm
minfmax 180 MHz 180 MHz 180 MHz 180 MHz 180 MHz
Load capacitance (CL) 14 pF 14 pF 14 pF - 14 pF
method of packing TUBE TUBE TR - TR
Maximum supply current (ICC) 12 mA 12 mA 12 mA - 12 mA

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