83021AMIT datasheet, PDF - EEWORLD Datasheet

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83021AMIT: DescriptionPECL to TTL Translator, 1 Func, True Output, PDSO8, 3.90 X 4.90 MM, 1.375 MM HEIGHT, MS-012, SOIC-8; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size648KB，12 Pages; ManufacturerIDT (Integrated Device Technology); Related ProductsFound19parts with similar functions to 83021AMIT

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83021AMIT Overview

PECL to TTL Translator, 1 Func, True Output, PDSO8, 3.90 X 4.90 MM, 1.375 MM HEIGHT, MS-012, SOIC-8

83021AMIT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	SOP, SOP8,.25
Contacts	8
Reach Compliance Code	not_compliant
ECCN code	EAR99
Other features	SUPPLY VOLTAGE 3.3 V ALSO POSSIBLE
maximum delay	2.5 ns
Interface integrated circuit type	PECL TO TTL TRANSLATOR
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Humidity sensitivity level	1
Number of digits	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output latch or register	NONE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm

83021AMIT Preview

1-TO-1 DIFFERENTIAL- TO-LVCMOS/LVTTL TRANSLATOR

ICS83021I

General Description

The ICS83021I is a 1-to-1 Differential-to-LVCMOS/

LVTTL Translator and a member of the

HiPerClockS™

HiPerClockS™ family of High Performance Clock

Solutions from IDT. The differential input is highly

flexible and can accept the following input types:

LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The small 8-lead

SOIC footprint makes this device ideal for use in applications with

limited board space.

Features

•

One LVCMOS/LVTTL output

Differential CLK/nCLK input pair

CLK/nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

Output frequency: 350MHz (typical)

Part-to-part skew: 500ps (maximum)

Additive phase jitter, RMS: 0.21ps (typical), 3.3V output

Full 3.3V and 2.5V operating supply

-40°C to 85°C ambient operating temperature

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

ICS

Block Diagram

CLK

Pulldown

nCLK

Pullup

Pin Assignment

CLK

nCLK

GND

ICS83021I

8-Lead SOIC, 150Mil

3.9mm x 4.9mm x 1.375mm package body

M Package

Top View

IDT™ / ICS™

LVCMOS/LVTTL TRANSLATOR

ICS83031AMI REV. C OCTOBER 31, 2008

ICS83021I

1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

Table 1. Pin Descriptions

Number

1, 4, 6

Name

CLK

nCLK

GND

Unused

Input

Power

Output

Power

Pulldown

Pullup

Type

Description

No connect.

Non-inverting differential clock input.

Inverting differential clock input.

Power supply ground.

Single-ended clock output. LVCMOS/LVTTL interface levels.

Positive supply pin.

NOTE:

Pullup and Pulldown

refer to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

PULLUP

PULLDOWN

OUT

Parameter

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Power Dissipation Capacitance

Output Impedance

= 3.6V

Test Conditions

Minimum

Typical

Maximum

Units

Ω

IDT™ / ICS™

LVCMOS/LVTTL TRANSLATOR

ICS83031AMI REV. C OCTOBER 31, 2008

ICS83021I

1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the

DC Characteristics or AC Characteristics

is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Supply Voltage, V

Inputs, V

Outputs, V

Package Thermal Impedance,

Storage Temperature, T

STG

Rating

4.6V

-0.5V to V

+ 0.5V

-0.5V to V

+ 0.5V

103°C/W (0 lfpm)

-65°C to 150°C

DC Electrical Characteristics

Table 3A. Power Supply DC Characteristics,

= 3.3V ± 0.3V or 2.5V ± 5%, T

= -40°C to 85°C

Symbol

Parameter

Positive Supply Voltage

2.375

Power Supply Current

2.5

2.625

Test Conditions

Minimum

3.0

Typical

3.3

Maximum

3.6

Units

Table 3B. LVCMOS/LVTTL DC Characteristics,

= 3.3V ± 0.3V or 2.5V ± 5%, T

= -40°C to 85°C

Symbol

Parameter

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Test Conditions

= 3.6V

= 2.625V

= 3.6V or 2.625V

Minimum

2.6

1.8

0.5

Typical

Maximum

Units

NOTE 1: Outputs terminated with 50Ω to V

/2. See Parameter Measurement Information,

Output Load Test Circuit Diagrams.

Table 3C. Differential DC Characteristics,

= 3.3V ± 0.3V or 2.5V ± 5%, T

= -40°C to 85°C

Symbol

Parameter

nCLK

Input High Current

CLK

nCLK

CMR

Input Low Cureent

CLK

Peak-to-Peak Input Voltage

Common Mode Input Voltage;

NOTE 1, 2

Test Conditions

= V

= 3.6V or 2.625V

= V

= 3.6V or 2.625V

= 0V, V

= 3.6V or 2.625V

= 0V, V

= 3.6V or 2.625V

-150

-5

0.15

GND + 0.5

1.3

– 0.85

Minimum

Typical

Maximum

150

Units

µA

NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V

+ 0.3V.

NOTE 2: Common mode voltage is defined as V

IDT™ / ICS™

LVCMOS/LVTTL TRANSLATOR

ICS83031AMI REV. C OCTOBER 31, 2008

ICS83021I

1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

AC Electrical Characteristics

Table 4A. AC Characteristics,

= 3.3V ± 0.3V, T

= -40°C to 85°C

Parameter

MAX

tsk(pp)

tjit

/ t

odc

Symbol

Output Frequency

Propagation Delay, NOTE 1

Part-to-Part Skew; NOTE 2, 3

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

Output Rise/Fall Time

Output Duty Cycle

100MHz, Integration Range

(637kHz – 10MHz)

0.8V to 2V

≤

166MHz

166MHz < ƒ

≤

350MHz

100

0.21

250

400

≤

350MHz

1.7

Test Conditions

Minimum

Typical

350

2.0

2.3

500

Maximum

Units

MHz

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at f

MAX

unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at V

/2.

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.

Using the same type of inputs on each device, the outputs are measured at V

/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Table 4B. AC Characteristics,

= 2.5V ± 5%, T

= -40°C to 85°C

Parameter

MAX

tsk(pp)

tjit

/ t

odc

Symbol

Output Frequency

Propagation Delay, NOTE 1

Part-to-Part Skew; NOTE 2, 3

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

Output Rise/Fall Time

Output Duty Cycle

100MHz, Integration Range

(637kHz – 10MHz)

20% to 80%

≤

250MHz

250MHz < ƒ

≤

350MHz

250

0.21

550

≤

350MHz

1.9

Test Conditions

Minimum

Typical

350

2.2

2.5

500

Maximum

Units

MHz

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

All parameters measured at f

MAX

unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output at V

/2.

NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.

Using the same type of inputs on each device, the outputs are measured at V

/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

IDT™ / ICS™

LVCMOS/LVTTL TRANSLATOR

ICS83031AMI REV. C OCTOBER 31, 2008

ICS83021I

1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

Additive Phase Jitter

The spectral purity in a band at a specific offset from the

fundamental compared to the power of the fundamental is called

the

dBc Phase Noise.

This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise power

present in a 1Hz band at a specified offset from the fundamental

frequency to the power value of the fundamental. This ratio is

expressed in decibels (dBm) or a ratio of the power in the 1Hz band

to the power in the fundamental. When the required offset is

specified, the phase noise is called a

dBc

value, which simply

means dBm at a specified offset from the fundamental. By

investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 100MHz

12kHz to 20MHz = 0.21ps (typical)

SSB Phase Noise dBc/Hz

Offset Frequency (Hz)

As with most timing specifications, phase noise measurements

has issues relating to the limitations of the equipment. Often the

noise floor of the equipment is higher than the noise floor of the

device. This is illustrated above. The device meets the noise floor

of what is shown, but can actually be lower. The phase noise is

dependent on the input source and measurement equipment.

IDT™ / ICS™

LVCMOS/LVTTL TRANSLATOR

ICS83031AMI REV. C OCTOBER 31, 2008

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83021AMIT Related Products

	83021AMIT	83021AMI
Description	PECL to TTL Translator, 1 Func, True Output, PDSO8, 3.90 X 4.90 MM, 1.375 MM HEIGHT, MS-012, SOIC-8	PECL to TTL Translator, 1 Func, True Output, PDSO8, 3.90 X 4.90 MM, 1.375 MM HEIGHT, MS-012, SOIC-8
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	SOIC	SOIC
package instruction	SOP, SOP8,.25	SOP, SOP8,.25
Contacts	8	8
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
Other features	SUPPLY VOLTAGE 3.3 V ALSO POSSIBLE	SUPPLY VOLTAGE 3.3 V ALSO POSSIBLE
maximum delay	2.5 ns	2.5 ns
Interface integrated circuit type	PECL TO TTL TRANSLATOR	PECL TO TTL TRANSLATOR
JESD-30 code	R-PDSO-G8	R-PDSO-G8
JESD-609 code	e0	e0
length	4.9 mm	4.9 mm
Humidity sensitivity level	1	1
Number of digits	1	1
Number of functions	1	1
Number of terminals	8	8
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output latch or register	NONE	NONE
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP
Encapsulate equivalent code	SOP8,.25	SOP8,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240	240
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	1.75 mm
Maximum supply voltage	2.625 V	2.625 V
Minimum supply voltage	2.375 V	2.375 V
Nominal supply voltage	2.5 V	2.5 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
width	3.9 mm	3.9 mm

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