Commercial
PEEL™ 16CV8 -25
CMOS Programmable Electrically Erasable Logic Device
Features
•
Compatible with Popular 16V8 Devices
- 16V8 socket and function compatible
- Programs with standard 16V8 JEDEC file
- 20-pin DIP, SOIC, TSSOP, and PLCC
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super sets standard 20-pin PLDs (PALs)
•
•
•
•
Multiple Speed, Power Options
- Speeds range 25ns
- Power as low as 37mA @ 25mHZ
Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software
- Automatic programmer translation and JEDEC file translation
software available for the most popular PAL devices
General Description
The PEEL
TM
16CV8 is a Programmable Electrically Erasable Logic
(PEEL) device providing an attractive alternative to ordinary PLDs. The
PEEL
TM
16CV8 offers the performance, flexibility, ease of design and
production practicality needed by logic designers today.
The PEEL
TM
16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP
packages (see Figure 1) with 25ns speed and power consumption as
low as 37mA. EE-Reprogrammability provides the convenience of
instant reprogramming for development and reusable production inven-
tory minimizing the impact of programming changes or errors. EE-
Reprogrammability also improves factory testability, thus assuring the
highest quality possible.
The PEEL
TM
16CV8 architecture allows it to replace over standard 20-
pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. ICT’s PEEL
TM
16CV8
can be programmed with existing 16CV8 JEDEC file. Some program-
mers also allow the PEEL
TM
16CV8 to be programmed directly from
PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional development
and programming support for the PEEL
TM
16CV8 is provided by popular
third-party programmers and development software. ICT also offers free
PLACE development software.
Figure 1 - Pin Configuration
I/CLK1
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/CLK1
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Figure 2 - Block Diagram
CLK
/CLK
PEEL
"AND"
ARRAY
64 TERMS
X
32 INPUTS
MACRO
CELL
DIP
I/CLK1
VCC
I/O
I/O
I/O
TSSOP
I/OE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3 2 1 20 19
I
I
I
I
I
4
5
6
7
8
9 10 11 12 13
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
I/CLK1
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
GND
I
I
I/O
PLCC-J
I/O
SOIC
1
04-02-004I
PEEL
TM
16CV8
Functional Description
The PEEL
TM
16CV8 implements logic functions as sum-of- products
expressions in a programmable-AND/fixed-OR logic array. User-defined
functions are created by programming the connections of input signals
into the array. User-configurable output structures in the form of macro-
cells further increase logic flexibility.
64 product terms:
-56 product terms (arranged in 8 groups of 7) form sum-of-product
functions for macrocell combinatorial or registered logic
-8 product terms (arranged 1 per macrocell) add an additional
product term for macrocell sum-of-products functions or I/O pin
output enable control
At each input-line/product-term intersection there is an EEPROM mem-
ory cell which determines whether or not there is a logical connection at
that intersection. Each product term is essentially a 32-input AND gate.
A product term which is connected to both the true and complement of
an input signal will always be FALSE and thus will not affect the OR
function that it drives. When all the connections on a product term are
opened, that term will always be TRUE.
When programming the PEEL
TM
16CV8, the device programmer first
performs a bulk erase to remove the previous pattern. The erase cycle
opens every logical connection in the array. The device is configured to
perform the user-defined function by programming selected connections
in the AND array. (Note that PEEL
TM
device programmers automatically
program all of the connections on unused product terms so that they will
have no effect on the output function.
Table 1 : PEEL
TM
16CV8 Device Compatibility
•
Architecture Overview
The PEEL
TM
16CV8 features ten dedicated input pins and eight I/O pins,
which allow a total of up to 16 inputs and 8 outputs for creating logic
functions. At the core of the device is a programmable electrically-eras-
able AND array which drives a fixed OR array. With this structure the
PEEL
TM
16CV8 can implement up to 8 sum-of-products logic expres-
sions.
Associated with each of the eight OR functions is a macrocell which can
be independently programmed to one of up to four different basic config-
urations. The programmable macrocells allow each I/O to create
sequential or combinatorial logic functions of active-high or active-low
polarity, while providing two possible feedback paths into the array.
Three different device modes, Simple, Complex, and Registered, sup-
port various user configurations. In Simple mode a macrocell can be
configured for combinatorial function with the output buffer permanently
enabled, or the output buffer can be disabled and the I/O pin used as a
dedicated input. In Complex mode a macrocell is configured for combi-
natorial function with the output buffer enable controlled by a product
term. In Registered mode, a macrocell can be configured for registered
operation with the register clock and output buffer enable controlled
directly from pins, or can be configured for combinatorial function with
the output buffer enable controlled by a product term. In most cases the
device mode is set automatically by the development software, based
on the features specified in the design.
The three device modes support designs created explicitly for the
PEEL
TM
16CV8, as well as designs created originally for popular PLD
devices such as the 16R4, 16R8, and 16L8. Table 1 shows the device
mode used to emulate the various PLDs. Design conversion into the
16CV8 is accommodated by JEDEC-to-JEDEC translators available
from ICT, as well as several programmers which can read the original
PLD JEDEC file and automatically program the 16CV8 to perform the
same function.
PLD Architecture
Compatibility
10H8
10L8
10P8
12H6
12L6
12P6
14H4
14L4
14P4
16H2
16HD8
16L2
16LD8
16P2
16H8
16L8
16P8
16R4
16R6
16R8
16RP4
PEEL
TM
16CV8
Device Mode
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Complex
Complex
Complex
Registered
Registered
Registered
Registered
AND/OR Logic Array
The programmable AND array of the PEEL
TM
16CV8 is formed by input
lines intersecting product terms. The input lines and product terms are
used as follows:
•
32 input lines:
-16 input lines carry the true and complement of the signals applied
to the 8 dedicated input pins
-16 additional lines carry the true and complement of 8 macrocell
feedback signals or inputs from I/O pins or the clock/ OE pins
2
04-02-004I
PEEL
TM
16CV8
Table 1 : PEEL
TM
16CV8 Device Compatibility
Simple Mode
In Simple mode, all eight product terms feed the OR array which can
generate a purely combinatorial function for the output pin. The pro-
grammable output polarity selector allows active-high or active-low logic,
eliminating the need for external inverters. For output functions, the
buffer can be permanently enabled. Feedback into the array is available
on all macrocell I/O pins, except for pins 15 and 16. Figure 6 shows the
logic array of the PEEL
TM
16CV8 configured in Simple mode.
Simple mode also provides the option of configuring an I/O pin as a ded-
icated input. In this case, the output buffer is permanently disabled, and
the I/O pin feedback is used to bring the input signal from the pin into the
logic array. This option is available for all I/O pins except pins 15 and 16.
Figure 3 shows the possible Simple mode macrocell configurations.
1
Simple Mode
Active Low Output
VCC
PLD Architecture
Compatibility
16RP6
14RP8
PEEL 16CV8
Device Mode
Registered
Registered
TM
Programmable Macrocell
The macrocell provides complete control over the architecture of each
output. The ability to configure each output independently permits users
to tailor the configuration of the PEEL
TM
16CV8 to the precise require-
ments of their designs.
Macrocell Architecture
Each macrocell consists of an OR function, a D-type flip-flop, an output
polarity selector, and a programmable feedback path. Four EEPROM
architecture bits MS0, MS1, OP, and RC control the configuration of
each macrocell. Bits MS0 and MS1 are global, and select between Sim-
ple, Complex, and Registered mode for the whole device. Bits OP and
RC are local for each macrocell; bit OP controls the output polarity and
bit RC selects between registered and combinatorial operation and also
specifies the feedback path. Table 2 shows the architecture bit settings
for each possible configuration.
Equivalent circuits for the possible macrocell configurations are illus-
trated in Figures 3, 4, and 5. When creating a PEEL
TM
device design,
the desired macrocell configuration generally is specified explicitly in the
design file. When the design is assembled or compiled, the macrocell
configuration bits are defined in the last lines of the JEDEC program-
ming file.
Table 2 : PEEL
TM
16CV8 Device Mode/Macrocell Configuration Bits
2
Simple Mode
Active High Output
VCC
3
Simple Mode
I/O Pin Input
Figure 3 - Macrocell Configurations for Simple mode of the PEEL
TM
16CV8 (see Figure 6 for Logic Array)
Config.
#
1
2
3
1
2
1
2
3
4
Mode
MSO
Simple
Simple
Simple
Complex
Complex
Registered
Registered
Registered
Registered
1
1
1
1
1
0
0
0
0
Architecture Bits
Function
MS1
0
0
0
1
1
1
1
1
1
OP
0
1
X
0
1
0
1
0
1
RC
0
0
1
1
1
0
0
1
1
Combinatorial
Combinatorial
None
Combinatorial
Combinatorial
Registered
Registered
Combinatorial
Combinatorial
Active Low
Active High
None
Active Low
Active High
Active Low
Active High
Active Low
Active High
I/O Pin
I/O Pin
I/O Pin
I/O Pin
I/O Pin
Registered
Registered
I/O Pin
I/O Pin
Polarity
Feedback
3
04-02-004I
PEEL
TM
16CV8
Complex Mode
In Complex mode, seven product terms feed the OR array which can
generate a purely combinatorial function for the output pin. The pro-
grammable output polarity selector provides active-high or active-low
logic, eliminating the need for external inverters. The output buffer is
controlled by the eighth product term, allowing the macrocell to be con-
figured for input, output, or bidirectional functions. Feedback into the
array for input or bidirectional functions is available on all pins except 12
and 19. Figure 4 shows the possible complex mode macrocell configura-
tions. Figure 7 shows the logic array of the PEEL
TM
16CV8 configured in
Complex mode.
1
Registered Mode
Active Low Registered Output
OE PIN
2
Registered Mode
Active High Registered Output
OE PIN
D
Q
Q
D
Q
Q
CLK PIN
CLK PIN
3
Registered Mode
Active Low Combinatorial Output
4
Registered Mode
Active High Combinatorial Output
PRODUCT TERM
PRODUCT TERM
1
Complex Mode
Active Low Output
2
Complex Mode
Active High Output
PRODUCT TERM
PRODUCT TERM
Figure 5 - Macrocell Configurations for the Registered Mode of
the PEEL
TM
16CV8 (see Figure 8 for logic Array)
Design Security
Registered Mode
Registered mode provides eight product terms to the OR array for regis-
tered functions. The programmable output polarity selector provides
active-high or active-low logic, eliminating the need for external invert-
ers. (Note, however, that if register is selected, the PEEL
TM
16CV8 reg-
Figure 4 - Macrocell Configurations for the Complex Mode of the
PEEL
TM
16CV8 (see Figure 7 for Logic Array)
isters power-up reset and so before the first clock arrives the output at
the pin will be low if the user has selected active-high logic and high if
the user has selected active-low logic. If combinatorial is selected, the
output will be a function of the logic.) For registered functions, the output
buffer enable is controlled directly from the /OE control pin. Feedback
into the array comes from the macrocell register. In Registered mode,
input pins 1 and 11 are permanently allocated as CLK and /OE, respec-
tively. Figure 8 shows the logic array of the PEEL
TM
16CV8 configured in
Registered mode.
Registered mode also provides the option of configuring a macrocell for
combinatorial operation, with seven product terms feeding the OR func-
tion.
Again the programmable output polarity selector provides active-high or
active-low logic. The output buffer enable is controlled by the eighth
product term, allowing the macrocell to be configured for input, output, or
bidirectional functions. Feedback into the array for input or bidirectional
functions is available on all I/O pins. Macrocell Configurations for the
Registered Mode of the PEEL
TM
16CV8
The PEEL
TM
16CV8 provides a special EEPROM security bit that pre-
vents unauthorized reading or copying of designs programmed into the
device. The security bit is set by the PLD programmer, either at the con-
clusion of the programming cycle or as a separate step, after the device
has been programmed. Once the security bit has been set it is impossi-
ble to verify (read) or program the PEEL
TM
until the entire device has
first been erased with the bulk-erase function.
Signature Word
The signature word feature allows a 64-bit code to be programmed into
the PEEL
TM
16CV8. The code cannot be read back after the security bit
has been set. The signature word can be used to identify the pattern
programmed into the device or to record the design revision, etc.
4
04-02-004I
PEEL
TM
16CV8
I
1
19
I/O
MACRO
CELL
I
2
MACRO
CELL
I
3
18
I/O
MACRO
CELL
I
4
17
I/O
MACRO
CELL
I
5
16
I/O
MACRO
CELL
I
6
15
I/O
MACRO
CELL
I
7
14
I/O
MACRO
CELL
I
8
13
I/O
MACRO
CELL
I
9
12
I/O
11
I
Figure 6 - PEEL
TM
16CV8 Logic Array - Simple Mode (see Figure 3 for macrocell details)
5
04-02-004I
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