This circuit is powered by the ADP1720
linear regulator (adjustable version), which regulates the loop supply to 2.5 V for the ADuC7060/ADuC7061, op amp
OP193 , and optional
ADR280 reference .
The 4 mA-20 mA feedback circuit is primarily controlled by the ADuC7060's on-chip 16-bit PWM (pulse width modulator). The duty cycle of the PWM is configured through software to control the voltage across the 47.5 ΩR
LOOP resistor, which in turn sets the loop current. Note that the top of R
LOOP is connected to the ADuC7060 ground and the bottom of R
LOOP is connected to the loop ground. Therefore, the current caused by the ADuC7060/ADuC7061, ADP1720, ADR280, and OP193, as well as the current set by the filtered PWM output, all flow through R
LOOP .
V
REF is provided by the ADR280, a 1.2 V precision voltage reference. Alternatively, the ADuC7060/ADuC7061's on-chip DAC can be configured to provide a 1.2 V reference voltage, but enabling the internal DAC results in additional power consumption.
The voltage at the junction of R1 and R2 can be expressed as:

when V
IN = 0, a full-scale current will be generated, and at this time V
RLOOP = V
REF . Therefore, the full-scale current is V
REF /R
LOOP , or approximately 24 mA. When V
IN = V
REF /2, no current flows. When
V
IN , the amplifier OP193 is in a high impedance state and does not constitute a load for the PWM filter output. The amplitude of the change in the amplifier output is very small, only about 0.7 V.
Performance at the range limits (0 mA to 4 mA and 20 mA to 24 mA) is irrelevant; therefore, the op amp does not need to perform well on the supply rails.
The absolute values of R1 and R2 don't matter. However, it should be noted that the matching of R1 and R2 is very important. Also note the possibility of
using the input channel of ADC0 on the ADuC7060/ADuC7061 to measure the voltage at
VR12 . This ADC measurement can be used as feedback for the PWM control software to adjust the 4 mA to 20 mA current settings.
The main ADC of the ADuC7060/ADuC7061 measures the voltage on the RTD. The RTD is excited by the on-chip excitation current source IEXC0. It is recommended to configure the excitation current to 200 μA to reduce power consumption, and it should be turned off during the measurement gap. The internal PGA gain of the main ADC front end is configured for 16 or 32. The reference source for RTD measurements can be an internal reference source or an external 5.62 kΩ reference resistor. Selecting an external resistor can further reduce power consumption. For more information on RTD to ADC interfacing and ADC result linearization techniques, please refer to Application Note AN-0970 and Circuit Note CN-0075.
The power requirements of this circuit depend on whether the temperature monitoring module is powered directly from the 4 mA to 20 mA loop supply or whether it is powered by a 4-wire active loop (the temperature monitoring module uses a separate power supply). This article assumes that the temperature monitoring module is powered by a loop power supply, so the total power consumption of the module should not exceed approximately 3.6 mA.
To support low-power operation, the internal POWCON0 register can be programmed to slow down the operation of the ADuC7060/ADuC7061 core. Its maximum frequency of 10.28 MHz can be divided by powers of 2 (2 to 128). The clock divider value used during testing was 16, which resulted in a core speed of 640 kHz. When the main ADC is enabled, the gain is 32. PWM can also be enabled. All other peripherals are disabled.
For our circuit and test setup, Table 1 details the power consumption of the IDD, and Table 2 lists the power consumption of various peripherals.
Table 1. Typical IDD Values for Components of Temperature Monitor Circuit
Component |
IDD Value
at 25°C |
IDD Value
at 85°C |
ADuC7060/ADuC7061
ADC0 On, Gain = 32, FADC = 100 Hz
CPU speed = 640 kHz
(POWCON0 = 0x7C)
PWM On. PWMCON1 = 0x100
External reference selected by ADC0.
All other peripherals off.
Note: Add excitation current value to
this figure . Typical value is 200 µA. |
2.45 mA
0.2 mA |
2.74 mA
0.2 mA |
ADR280, 1.2 V Reference |
12 µA |
15 µA |
ADP1720, 2.5 V Output Linear Regulator |
200 µA 3 |
300 µA |
OP193, Low Power Op Amp |
15 µA |
25 µA |
Remaining Circuitry |
50 µA |
50 µA |
Total Current Less Excitation Current |
2.73mA |
3.13mA |
The DNL plot in Figure 2 shows that DNL is typically better than 0.6 LSB over the critical 4 mA to 20 mA range. These tests employ a second-order filter at the PWM output and use two 47 kΩ resistors and two 100 nF capacitors, as shown in Figure 1.
Figure 2. Typical DNL performance of circuit
The performance of the PWM output can be enhanced by using the ADC to measure the voltage at point V R12 and other points in the circuit. This feedback method can be used to calibrate the PWM output to provide higher accuracy.
Note that the PWM circuit is only used to set the output voltage in the range of 0 V to 600 mV, so the code count is reduced. Codes above 0 represent values greater than 24 mA and are therefore irrelevant.
For ADC measurement performance, please refer to the AN-970, CN-0075, and ADuC7060/ADuC7061 data sheets.
Table 2. Typical IDD Values for Different Peripherals on the ADuC7060/ADuC7061
Peripheral of ADuC7060/61 |
DD Value, Typical, 25°C |
ARM7 Core @ 10.24 MHz
5.12 MHz
2.56 MHz
1.28 MHz
640 kHz
320 kHz
160 kHz
80 kHz |
5.22 mA
4.04 mA
2.7 mA
2 mA
1.674 mA
1.5 mA
1.42 mA
1.38 mA |
Primary ADC, G = 1
G = 4
G ≥ 128 |
30 µA
440 µA
630 µA |
Auxiliary ADC |
350 µA |
DAC |
330 µA |
PWM |
340 µA |
SPI |
40 µA |
UART |
200 µA |