Figure 1 shows a high-performance industrial signal-level multi-channel data acquisition circuit optimized for fast channel-to-channel switching. The circuit can handle 16 channels of single-ended inputs or 8 channels of differential inputs with up to 18-bit resolution.

Single channel sampling rate is up to 1.33 MSPS with 18-bit resolution. Channel-to-channel switching rate for all input channels is 250 kHz, with 16-bit performance.

Signal processing circuitry combined with a simple 4-bit up/down binary counter provides a simple, cost-effective solution for switching between channels without the need for FPGAs, CPLDs, or high-speed processors. The counter can be set programmably to count up or down to achieve sequential sampling of multiple channels; a fixed binary word can also be loaded for single-channel sampling.

This circuit is an ideal solution for multi-channel data acquisition cards that can be used in a variety of industrial applications, including process control and power line monitoring.

The circuit in Figure 1 is a classic multi-channel asynchronous data acquisition signal chain, consisting of a multiplexer, amplifier and ADC.

This architecture allows fast sampling of multiple channels using a single ADC, with low cost and excellent channel-to-channel matching performance.

Channel-to-channel switching speed is limited by the settling time of multiple elements in the signal chain after the multiplexer, which generates full-scale step voltage outputs for downstream amplifiers and ADCs. The components of this circuit have been carefully selected to minimize settling time and increase switching speed between channels.

Device selection

The ADG5208 multiplexer switches one of the eight inputs to a common output based on the address determined by the 3-bit binary address line. The ADG5236 contains two independently selectable single-pole double-throw (SPDT) switches. Two ADG5208 switches combined with an ADG5236 allow 16 single-ended channels or 8 true differential channels to connect to the rest of the signal chain via a 4-bit digital control signal.

The 4-bit digital signal is generated by a 4-bit binary up/down counter whose trigger signal is the same signal as the conversion (CNV) input of the 18-bit, 1.33 MSPS AD7984 ADC.

The AD8065 JFET input op amp has a bandwidth of 145 MHz and is configured as a unity gain buffer, providing excellent settling time performance and very high input impedance. The AD8065 also provides a very low impedance output that drives the attenuation stage of the AD8475 funnel amplifier.

A fully differential signal chain offers the following advantages: good common-mode rejection and fewer second-order distortion products. In order to process ±10 V industrial level signals with modern low voltage differential input ADCs, it is necessary to use attenuation and level shifting stages.

The AD8475 is a fully differential attenuation (funnel) amplifier with integrated precision gain resistors, providing 0.4x or 0.8x precision attenuation, common-mode level conversion, single-ended to differential conversion, and input overvoltage protection. The fast settling time (0.001% settling time of 50 ns) and low noise performance (10 nV/√Hz) make the AD8475 ideal for driving 18-bit differential input ADCs with sampling rates up to 4 MSPS.

This circuit selected the AD7984, an 18-bit PulSAR® ADC that provides 18-bit resolution at 1.33 MSPS when sampling a single channel. However, when switching channels sequentially, the settling time of various components in the signal chain limits overall accuracy. For example, 16-bit performance when switching between channels at 250 kHz.

For a detailed timing and noise analysis of the circuit, please refer to the CN0269 PDF . 

Test result histogram

Figure 16 shows a histogram of test results for 10,000 samples. During the test, the 16 single-ended channels were shorted together and connected to the GND of the PCB. Note that the peak-to-peak noise is approximately 12 LSB, including the input buffer.

Communicate test results

AC performance testing was performed at the system level with the AD7984 sampling at 300 kSPS and a 2.5 V peak-to-peak, 10.675 kHz input sine wave signal provided by a 1051 B&K sine generator. The circuit samples continuously on channel 4, excluding the effects of the input buffer. FFT shows SNR = 91.33 dBFS.

Switching speed and settling time test results

The following graph shows settling time performance. The laboratory test setup is shown in Figure 18.

The CN-0269 evaluation board is configured in 16-channel single-ended input mode, with 8 odd-numbered channels shorted together and 8 even-numbered channels shorted together.

An array of cells is used to generate different DC input voltages for low noise and low impedance performance.

Odd and even channels are connected to different voltages. LabVIEWTM software controls the parameters between EVAL-SDP-CB1Z and continuously switches between input channels. Switching rates range from 100 Hz to 1 MHz in 1 kHz increments. Take 10 samples at each switching rate and average the results. The average value with the lowest switching rate is used as the reference point. The error at each switching rate is calculated by taking the difference between the 10 samples and the reference value. The test results are shown in Figure 19 and Figure 23.

In the figure, a 2 LSB error corresponds to a 17-bit settling time, while a 4 LSB error corresponds to a 16-bit settling time.

As shown in the figure above, it can be seen that at switching rates below 1 MHz, the circuit with the input buffer has better settling time performance than the circuit without the pre-buffer.

Figure 21, Figure 22, and Figure 23 show the circuit settling to 16 bits at channel-to-channel switching rates above 250 kHz with the input buffer connected.