The circuit shown in Figure 1 is a single-supply, low-power, window detector with programmable upper and lower limits. This type of circuit can be used to generate an alarm if the signal exceeds preset limits and is popular in detection and monitoring applications. The AD5668-1 eight-channel, low-power, 16-bit, buffered voltage output DAC is used to set the window limits. The AD5668-1 contains an on-chip 1.25 V, 5 ppm/°C voltage reference with a full-scale output range of 0V to 2.5V. The internal voltage reference is enabled via a software write. The SPI interface is used to communicate with the AD5668-1 .

The comparator used is the ADCMP370 general-purpose, low-power comparator (20W at 5 V, typical) with a 9 mV input offset voltage (max) and an open-drain output.

The circuit shown in Figure 1 is an upper and lower programmable window detector. The upper and lower limits are loaded into each DAC register individually. The primary application of this circuit is to test whether an external signal falls within programmed limits.

The AD5668-1 is an eight-channel DAC with upper and lower limits set on the outputs on channel A and channel B respectively.

For testing purposes, DAC C provides signal input. When the signal enters the region set by DACA and DAC B, the voltage on TP1 changes to logic 1, LED1 turns off, and LED2 turns on. When the signal exceeds the window set by the upper and lower limits, LED1 turns on and LED2 turns off.

If you connect a pull-up resistor to the output of the ADCMP370 , if the non-inverting input is greater than the inverting input, the output will be 5 V; otherwise, the output will be 0 V.

The ADCMP370 has an open-drain output, allowing the outputs of comparators C1 and C2 to be connected together in a "wired AND" manner. Table 1 shows the truth table for this circuit. In this example, VOUTA is the upper limit, VOUTB is the lower limit, and VOUTA > VOUTB.

The working principle of the circuit is shown in Figure 2. DAC C generates a 0 V to 2.5 V triangular waveform that drives the VINC (TP2/TESTC) input to the comparator. The threshold level is set by DAC A (VOUTA = 2 V) and DAC B (VOUTB = 1 V). When the VINC voltage is between the two thresholds, the voltage on TP1 becomes a logic 1.