The circuit shown in Figure 1 is an integrated 3-wire resistance temperature detector (RTD) system based on the AD7124-4 / AD7124-8 low-power, low-noise, 24-bit Σ-Δ analog-to-digital converter (ADC). Optimized for high-precision measurement applications. Using two-point calibration and linearization, the overall accuracy of the 3-wire system is better than ±1°C over the temperature range of −50°C to +200°C. In full power mode, sinc4 filter selected, and output data rate of 50 SPS, the system

 

The AD7124-4 can be configured for 4 differential or 7 pseudo-differential input channels, while the AD7124-8 can be configured for 8 differential or 15 pseudo-differential input channels. The on-chip programmable gain array (PGA) ensures that small signals can be input directly into the ADC.

The AD7124-4/AD7124-8 offer the highest level of signal chain integration and include programmable low-drift excitation current sources. Most of the building blocks required for an RTD measurement system are integrated on-chip, thus greatly simplifying RTD system design.

The AD7124-4/AD7124-8 allow the user the flexibility to use one of three integrated power modes, with current consumption, output data rate range, and rms noise corresponding to the selected power mode. In low power mode, the AD7124-4/AD7124-8 consumes only 255 μA and 930 μA in full power mode. These power options make the device suitable for both applications where power consumption is not critical, such as input/output modules, and low-power applications, such as loop-powered smart transmitters (the entire transmitter must consume less than 4 mA ).

The device also has a shutdown option. In shutdown mode, the entire ADC and its auxiliary functions are shut down, reducing typical power consumption of the device to 1 μA. The AD7124-4/AD7124-8 also integrate rich diagnostic capabilities as part of a comprehensive feature set.

Introduction to RTD Temperature Measurement

RTDs are commonly used sensors for temperature measurement in industrial applications. RTDs are made of pure metals such as platinum, nickel, or copper, and their resistance changes predictably with temperature. The most commonly used RTDs are platinum Pt100 and Pt1000. Compared with other types of temperature sensors, RTDs have high accuracy and good stability. The resistance of long wires can be compensated using a 3-wire connection.

To accurately measure resistance, a constant current source is used to generate a voltage across the RTD. The AD7124-4/AD7124-8 provide two of these excitation current sources, which are register programmable to values ​​from 50 μA to 1 mA. Errors in the current source can be easily eliminated by reducing the measured value to the voltage across a precision reference resistor (driven by the same current), resulting in a ratiometric measurement.

The circuit shown in Figure 1 uses a Class B Pt100 RTD sensor. The temperature measurement range of the Pt100 RTD is −200°C to +600°C. A Class B RTD has a typical resistance of 100 Ω at 0°C and a typical temperature coefficient of about 0.385 Ω/°C (see Figure 2). Using this information, it is easy to calculate the voltage developed across the Pt100 RTD based on the selected current source.

 

How the circuit works

The AD7124-4/AD7124-8 provide an integrated RTD measurement solution that achieves high resolution, low nonlinearity error, low noise performance, and extremely high 50 Hz/60 Hz rejection. The AD7124-4/AD7124-8 integrates a low-noise PGA on-chip, which can amplify the small signal of the RTD. The gain programming range is from 1 to 128, so it can be directly interfaced with the sensor. The gain stage has a high input impedance and input leakage current does not exceed 3.3 nA in full power mode and 1 nA (typ) in low power mode. The following explains the different components that make up a 3-wire RTD temperature measurement system.

power supply

The AD7124-4/AD7124-8 feature separate analog and digital supplies. The digital supply IOVDD is independent of the analog supply and can have values ​​in the range 1.65 V to 3.6 V (referenced to DGND). Analog power supply AVDD is referenced to AVSS and ranges from 2.7 V to 3.6 V (low and medium power mode) or 2.9 V to 3.6 V (full power mode). The circuit shown in Figure 1 operates from a single supply, so AVSS is connected to DGND, using only one ground plane. The AVDD and IOVDD voltages are generated separately using the ADP1720 voltage regulator. The AVDD voltage is set to 3.3 V and the IOVDD voltage is set to 1.8 V using an ADP1720 voltage regulator. Using a separate voltage regulator ensures minimal noise.

Serial Peripheral Interface (SPI)

SPI communication with the AD7124-4/AD7124-8 is handled by the Blackfin® ADSP-BF527 on the EVAL-SDP-CB1Z board , as shown in Figure 1. To access the registers of the AD7124-4/AD7124-8, use the AD7124-4/AD7124-8 EVAL+ software . Figure 3 shows the main window of the software. Click the 3-WIRE RTD button to configure the software for 3-wire RTD measurements.

 

The AD7124-4/AD7124-8 have on-chip diagnostics that can be used to detect SPI communication failures. These diagnostics include checking SPI read and write operations to ensure that only valid registers are accessed. The SCLK counter ensures that the correct number of SCLK pulses is used, while the CRC function checks whether the bit value changed during the transfer. When any SPI communication diagnostic function is enabled and a related error occurs, the corresponding flag in the error register will be set to 1. All enabled flags are ORed together to control the ERR flag in the status register. This feature is particularly useful when appending status bits to ADC conversion results.

Analog inputs and voltage references

The AD7124-4 can be configured as 4 differential or 7 pseudo-differential channels, while the AD7124-8 can be configured as 8 differential or 15 pseudo-differential channels.

The AD7124-4/AD7124-8 have on-chip diagnostics that can be used to check whether the levels on the analog pins are within the specified operating range. The positive (AINP) and negative (AINM) analog inputs can be independently checked for overvoltage and undervoltage occurrences, as well as for ADC saturation. When the voltage on the analog input exceeds AV _DD , the overvoltage flag is set; when the voltage on the analog input is lower than AV _SS , the undervoltage flag is set.

The circuit shown in Figure 1 implements 3-wire measurements using four analog pins: AIN0, AIN1, AIN2, and AIN3. AIN2 and AIN3 are configured as fully differential input channels for sensing the voltage on the Pt100. The excitation current source used to excite the RTD is generated by AV _DD and flows to AIN0. An identical current flows to AIN1 and through the RL2 lead resistor, creating a voltage that cancels the voltage drop across the RL1 lead resistor. Figure 4 shows the analog pins and their configuration in detail.

 

When the PGA is enabled, the analog input buffer is automatically enabled. The PGA allows voltages on the input pins as low as AV _SS , therefore, no headroom resistors are required on the analog input pins. The reference buffer is also enabled. These buffers require headroom. The reference resistor is on the high side and its headroom requirements are met, so no other headroom resistors are needed. For the circuit shown in Figure 1, the reference input used is REFIN1(±). The current flowing through Pt100 will also flow through the precision reference resistor, generating a reference voltage. The voltage developed across this precision reference resistor is proportional to the voltage across the Pt100, so errors caused by fluctuations in the excitation current are eliminated.

Digital and analog filtering

差分滤波器（截止频率约为800 Hz）和共模滤波器（截止频率约为16 kHz）在模拟输入端和基准输入端实现。 为了抑制调制器频率及其倍数处的干扰，必须使用这种滤波。

AD7124-4/AD7124-8在片内数字滤波方面拥有很大的灵活性。 有多种滤波器选项可用，所选的滤波器会影响输出数据速率、建立时间和50 Hz/60 Hz抑制性能。 对于此电路笔记，电路实现了sinc⁴滤波器和后置滤波器。 之所以使用sinc⁴滤波器，是因为它在整个输出数据速率范围内具有出色的噪声性能，另外还有出色的50 Hz/60 Hz抑制性能。 后置滤波器用于提供50 Hz和60 Hz同时抑制，建立时间为40 ms。

校准

AD7124-4/AD7124-8提供不同的校准模式，通过校准可消除失调和增益误差。对于本电路笔记，电路使用了内部零电平校准和内部满量程校准。 注意，这些校准只能消除ADC增益和失调误差，而不能消除外部电路引起的增益和失调误差。

3线RTD配置

图1所示电路使用AD7124-4/AD7124-8进行精密3线RTD测量。 3线RTD测量需要两个精密激励电流源，以便轻松消除RL1和RL2产生的引线电阻误差。 注意，RL3引线电阻不会影响测量精度。 对于图1所示3线RTD配置，基准电阻放在RTD的高端。 对于此设置，一个激励电流流经基准电阻和RTD；另一个电流流经引线电阻RL2，其产生的电压抵消RL1上的压降。 由于仅利用一个激励电流来产生基准电压REFIN1±和RTD上的电压，因此，该电流源的精度、失配和失配漂移对ADC传递函数的影响极小。

激励电流在Pt100 RTD上产生一个低电平电压。 此低电平电压由AD7124-4/AD7124-8的片上PGA放大，然后通过24位Σ-Δ ADC转换为精密数字信号。 对于此3线RTD配置，两个激励电流均设置为500 µA。 对于最高600℃的RTD温度，采用500 μA激励电流时，RTD上产生的电压约为156.85 mV。

为确保使用AD7124-4/AD7124-8的最大范围，PGA增益设置为16，其将RTD传感器最大输出电压放大到2.5096 V。 为确保此3线电路实现真正的比率式配置，ADC的基准电压利用外部精密电阻产生，所用的激励电流与Pt100情况相同。 使用这种配置意味着，激励电流值的任何波动都会反映在Pt100和基准电阻上，因而不会改变系统的精度。

使用500 µA激励电流和ADC的放大电压，基准电阻值为：

因此，选择5.11 kΩ电阻，其产生的基准电压为：

利用AD7124-4/AD7124-8进行3线RTD测量时，还必须考虑激励电流源的输出顺从电压。 输出顺从电压取决于所选的激励电流。 本电路选择500 μA，其输出顺从电压为AV_DD− 0.37 V。 本电路的AV_DD电源电压为3.3 V，因此，激励电流源的输出顺从电压必须低于2.93 V。 从上述计算可知，电路满足这一要求，因为AIN0引脚的最大电压等于精密基准电阻上的电压加上RTD上的电压：

针对3线RTD测量的AD7124-4/AD7124-8配置如下：

• 差分输入： AINP = AIN2，AINM = AIN3
• 激励电流： IOUT0 = AIN0 = 500 μA
• 激励电流： IOUT1 = AIN1 = 500 μA
• 增益= 16
• 5.11 kΩ 精密基准电阻
• 数字滤波（sinc⁴和后置滤波器）

当ADC工作在双极性模式时，计算RTD电阻(R)的通用表达式如下所示：

其中：

CODE为ADC码。
N为ADC的分辨率（本电路为24）。
R_REF 为基准电阻。
G为所选增益。

根据B类RTD的规格，电阻变化约为0.385 Ω/℃。 可利用此关系快速获得RTD的近似温度。 由于RTD的温度系数在整个温度范围内略有变化，因此上述方法不够精确，但可以利用它来快速检查温度。

使用公式2计算近似温度，RTD电阻在0℃时为100 Ω。

RTD传递函数即所谓Callender-Van Dusen公式，它由两个不同的多项式公式组成。 公式3用于0℃以上的温度，公式4用于0℃以下的温度。

温度t ≤ 0℃时，公式为：

温度t ≥ 0℃时，公式为：

其中：

t 为RTD温度(℃)。
R_RTD(t) 为RTD在温度(t)时的电阻(Ω)。
R₀ 为0℃时的RTD电阻（本例中R₀= 100 Ω）。
A = 3.9083 × 10⁻³.
B = −5.775 × 10⁻⁷.
C = −4.23225 × 10⁻¹².

结合公式3和公式4给出的传递函数，有多种方法可以确定作为RTD电阻函数的温度值。 本电路笔记选择直接数学方法，因为其精度高。 根据公式3可得出以下温度计算公式：

其中 r为RTD电阻，其它变量的定义如上所述。

此方法能够很好地处理大于或等于0℃的温度。 计算0℃以下的RTD温度需要使用最佳拟合多项式表达式。 本电路笔记使用的多项式为五阶多项式，如公式6所示。

举例来说，温度设置为25℃时，若从AD7124-4/ AD7124-8读出的代码为11270065，则利用公式1将其转换为电阻值：

利用公式5进行线性化，得出温度为24.921℃。

再举一例，温度设置为−25℃时，若从AD7124-4/AD7124-8读出的代码为10757779，则将其转换为电阻值：

利用公式6进行线性化，得出温度为−24.982℃。

3线RTD测量和结果

对于图1所示电路，我们采集了AD7124-4/AD7124-8在不同数字滤波器和功耗模式配置下获得的数据，sinc⁴滤波器用于全功率模式，后置滤波器用于低功耗模式。

The AD7124-4/AD7124-8 operate with optimal speed and noise performance when the sinc ⁴ filter, full power mode, and 50 SPS output data rate configurations are selected. Figure 5 shows the noise distribution at room temperature for a 3-wire RTD when connected as shown in Figure 1. The corresponding root mean square noise is typically 199.37 nV rms, which is equivalent to approximately 17.9 bits of noise-free resolution. Selecting the same filter, gain, and output data rate, but with the input shorted, the noise performance of the AD7124-4/AD7124-8 is typically 100 nV rms, equivalent to 18.7 bits of noise-free resolution. The increase in noise comes directly from the RTDs connected on the input channels (AIN2, AIN3).

 

For a 3-wire RTD configuration with sinc ⁴ filter and full power mode selected, the RTD temperature is swept from −50°C to +200°C. For each temperature, measure the corresponding voltage on the RTD using the AD7124-4/AD7124-8 as described above. This voltage is then converted to resistance, linearized and converted to temperature as described in the "3-Wire RTD Configuration" section. Figure 6 shows the error between the set temperature and the RTD measured system temperature after linearization. The AD7124-4/AD7124-8 maintain 25°C for each RTD temperature setting. As shown in Figure 6, the error of the RTD's measured temperature is within the error window of the Pt100 Class B RTD. Figure 6 also shows the deviation of the RTD error at different AD7124-4/AD7124-8 temperature settings. For each temperature setting of the AD7124-4/AD7124-8, internal zero-scale calibration and full-scale calibration are performed. As shown in Figure 6, the RTD error is within the expected error range for a Class B RTD for all temperature settings of the AD7124-4/AD7124-8.

 

Figure 7 shows the measured temperature error of the RTD after performing a one-time internal zero-scale and full-scale calibration at 25°C. This graph shows that the AD7124-4/AD7124-8 exhibit similar performance when performing a one-time calibration at 25°C versus performing calibration at various temperature settings.

 

The second AD7124-4/AD7124-8 configuration tested was low power mode with the post filter selected and the 25 SPS output data rate. The 25 SPS filter provides simultaneous 50 Hz and 60 Hz rejection and allows the user to trade settling time for power supply rejection performance. Figure 8 shows the noise distribution of a 3-wire RTD at room temperature when connected as shown in Figure 1. The corresponding root-mean-square noise is typically 774 nV rms, equivalent to approximately 16.8 bits of noise-free resolution. Using the same filters, gains, power modes, and output data rates, but with the input shorted, the AD7124-4/AD7124-8 have a typical noise performance of 360 nV rms, equivalent to 17.3 bits of noise-free resolution. The noise increase for both measurements comes directly from the RTD connections on the input channels (AIN2, AIN3).

 

For the AD7124-4/AD7124-8 configuration with post filter and low power mode selected, the RTD temperature is swept from −50°C to +200°C. For each set RTD temperature, measure the corresponding voltage on the RTD using the AD7124-4/AD7124-8 as described above. This voltage is then converted to resistance, linearized and converted to temperature as described in the "3-Wire RTD Configuration" section. Figure 9 shows the error between the set temperature and the RTD measured temperature after linearization. The AD7124-4/AD7124-8 maintain 25°C for each RTD temperature setting. As shown in Figure 9, the error of the RTD's measured temperature is within the error window of the Pt100 Class B RTD. Figure 9 also shows the deviation of the RTD error at different AD7124-4/AD7124-8 temperature settings. For each temperature setting of the AD7124-4/AD7124-8, internal zero-scale calibration and full-scale calibration are performed. Figure 9 shows that the RTD error is within the expected error range for a Class B RTD for all temperature settings of the AD7124-4/AD7124-8.

 

Figure 10 shows the measured temperature error of the RTD after performing a one-time internal zero-scale and full-scale calibration at 25°C. This graph shows that the AD7124-4/AD7124-8 exhibit similar performance when performing a one-time calibration at 25°C versus performing calibration at various temperature settings.