High-side current monitors may experience overvoltage conditions after a transient, or when the monitoring circuit is connected, disconnected, or turned off. The circuit shown in Figure 1 uses an ADA4096-2 op amp with overvoltage protection connected as a differential amplifier to monitor high-side current. The ADA4096-2 has input overvoltage protection so that no inversion or latch-up will occur up to 32 V above or below the supply rail.

The circuit is powered by the ADP3336 adjustable low dropout 500 mA linear regulator , which can also be used to power other components in the system if required. When set to 5 V output, the input voltage range is 5.2 V to 12 V. To save power, the current sensing circuit can be turned off by removing the ADP3336 power supply, while the power source (such as a solar panel) can still operate.

This voltage will be applied to the unpowered ADA4096-2 input; however, no latch-up or damage will occur for input voltages within 32 V of the supply rails. For lower throughput rates, the AD7920 can also sleep between samples. The maximum power consumption of the AD7920 is 5 ¬W in sleep and 15 mW when powered up. Under operating conditions, the ADA4096-2 requires only 120 μA. When the operating voltage is 5 V, the power consumption is only 0.6 mW. In shutdown mode, the ADP3336 consumes only 1 μA.

This circuit is a classic high-side current sensing circuit topology using a single sense resistor. The other four resistors (dual 1 kΩ/20 kΩ divider) are within the membrane network (for ratio matching) and set the differential amplifier gain. This amplifies the difference between the two voltages developed across the sense resistor and suppresses the common-mode voltage:

V _OUT = (V _A – V _B ) (20 kΩ/1 kΩ)

Figure 2 shows the schematic diagram of the ADA4096-2. The input stage contains two parallel differential pairs (Q1 to Q4 and Q5 to Q8). As the input common-mode voltage approaches V _cc -1.5 V, Q1 through Q4 turn off when I1 reaches the minimum compliance voltage. Conversely, as the input common-mode voltage approaches V _EE + 1.5 V, Q5 through Q8 turn off when I2 reaches its minimum compliance voltage. This topology achieves maximum input dynamic range because the amplifier can handle the input at 200 mV outside the supply rail (room temperature).

_{As with any rail-to-rail input amplifier, the V OS} mismatch between the two input pairs determines the amplifier's CMRR. If the input common-mode voltage range is kept within 1.5 V of each supply rail, transitions between input pairs can be avoided, improving CMRR by approximately 10 dB.

The ADA4096-2 input protects the device from input voltage excursions up to 32 V beyond each supply rail. This feature is particularly important in applications with power supply sequencing issues that can cause the signal source to become active before amplifier power is applied.

Figure 3 shows the input current limiting capability of the ADA4096-2 provided by a low RDSON internal series FET (green curve) compared to using an external 5 kΩ series resistor and an unprotected op amp (red curve).

Figure 3 shows the ADA4096-2 in a unity-gain buffer configuration, where the supply is connected to GND (or ±15 V) and the positive input is swept until the input exceeds the supply by 32 V. Generally, the input current is limited to 1 mA during positive overvoltage conditions and 200 µA during negative undervoltage conditions. For example, under a 20 V overvoltage condition, the ADA4096-2 input current is limited to 1 mA, providing a current limit equivalent to a series 20 kΩ resistor.

Figure 3 also shows that the current limit circuit is effective whether or not the amplifier is powered.

Please note that Figure 3 only represents input protection under abnormal conditions. See Table 2 through Table 4 of the ADA4096-2 data sheet for the correct amplifier operating input voltage range (IVR).

The AD7920 is a 12-bit, high speed, low power successive approximation ADC that operates from a single 2.35 V to 5.25 V supply and has a maximum throughput of 250 kSPS. The device contains a low-noise, wide-bandwidth sample-and-hold amplifier that can handle input frequencies above 13 MHz.

The conversion process and data acquisition process are controlled through CS and the serial clock SCLK, thereby creating conditions for the device to interface with a microprocessor or DSP. The input signal is sampled on the falling edge of CS , where conversion is simultaneously initiated. The device has no pipeline delays.

AD7920 uses advanced design technology to achieve extremely low power consumption at the following high throughput rates. To enter shutdown mode, it must be at any time after the second falling edge of SCLK and before the 10th falling edge. Bring CS high to interrupt the conversion process. Once CS goes high within this window of SCLK, the device enters shutdown mode, the conversion initiated by the falling edge of CS is terminated, and SDATA returns to three-state. If CS goes high before the 2nd SCLK falling edge, the device will still be in normal mode and will not shut down. This avoids glitches on the CS line causing unexpected shutdown.

To exit this operating mode and power up the AD7920 again, a pseudo conversion needs to be performed. The device begins powering up on the falling edge of CS and continues to power up as long as CS is low until after the 10th SCLK falling edge. After 16 SCLKs, the device is fully powered up and the next conversion will produce valid data.

If CS goes high before the 10th SCLK falling edge, the AD7920 returns to shutdown mode again. This avoids glitches on the CS line causing unexpected power-ups, or unexpected bursts of 8 SCLK cycles when CS is low. Although the device can start powering up on the falling edge of CS , it will shut down again on the rising edge of CS as long as it does not exceed the 10th SCLK falling edge .

See the AD7920 data sheet for timing details.

Test Results

An important measure of the performance of this circuit is the amount of noise in the final output voltage measurement.

Figure 4 shows a histogram of 10,000 measured samples. This data was obtained using the CN-0241 evaluation board connected to the EVAL-SDP-CB1Z System Demonstration Platform (SDP-B) evaluation board . See the "Circuit Evaluation and Testing" section of this circuit note for setup details.

The power supply was set to 3.0 V, the output of the LDO was not turned off, and 10,000 data samples were acquired at a maximum rate of 250 kSPS. Figure 4 shows the acquisition results. The peak-to-peak noise is approximately 2 LSB, which corresponds to approximately 0.3 LSB rms.

Then set the SD shutdown pin connected to the ADP3336 low in software to turn off the LDO output. After about 1 minute, set the shutdown pin of ADP3336 to high level, reopen the output, and collect the same number of data samples. Figure 5 shows the acquisition results.

Figure 5 shows that the output of the ADA4096-2 does not latch during shutdown when the input is high.

For the complete design support package for this circuit note, see www.analog.com/CN0241-DesignSupport .