3228

CN0213

Complete high-speed, high common-mode rejection ratio (CMRR) precision analog front end for process control applications

 
Overview

Circuit functions and advantages

Signal levels in industrial process control systems typically fall into one of the following categories: single-ended current (4 mA to 20 mA), single-ended differential voltage (0 V to 5V, 0 V to 10 V, ±5 V, ±10 V) or a small signal input from a sensor such as a thermocouple or load cell. Large common-mode voltage swings are also typical, especially for small-signal differential inputs; therefore, good common-mode rejection is an important feature of analog signal processing systems.

The analog front-end circuit shown in Figure 1 is optimized to provide high accuracy and high common-mode rejection ratio (CMRR) when processing these types of industrial-grade signals.

Figure 1: High-performance analog front-end for process control applications (schematic: all connections and decoupling not shown)

 

This circuitry level shifts and attenuates the signal so that it is compatible with the input range requirements of most modern single-supply SAR ADCs, such as the high-performance, 16-bit 250 kSPS PulSAR® ADC AD7685 .

For an input signal of 18 V pp, the circuit's common-mode rejection (CMR) performance is approximately 105 dB at 100 Hz and 80 dB at 5 kHz.

High accuracy, high input impedance, and high CMR are provided by the AD8226 instrumentation amplifier . For high-precision applications, high input impedance is required to minimize system gain error and achieve excellent CMR. The AD8226 gain is programmable with resistors in the range of 1 to 1000.

Connecting a resistive level shifter/attenuator stage directly to the input will degrade CMR performance due to mismatch between the resistors. The AD8226 provides excellent CMR performance required for both small and large signal inputs. The AD8275 level shifter/attenuator/driver performs the attenuation and level shifting functions in this circuit without the need for any external components.

Σ-Δ ADCs are often used in high-resolution measurement systems due to their relatively low signal bandwidth, and the Σ-Δ architecture can provide excellent noise performance at low update rates. However, in an increasing number of designs, especially multi-channel systems, the update rate is increasing to update individual channels faster or to increase channel density. In this case, high-performance SAR ADC is a good alternative. The circuit shown in Figure 1 uses the AD7685 250 kSPS 16-bit ADC, the AD8226 high-performance instrumentation amplifier, and the AD8275 attenuator/level converter/amplifier and is configured as a complete system solution without any external components.

Circuit description

This circuit incorporates a rail-to-rail output instrumentation amplifier AD8226 and is connected to the positive input of a G = 0.2 differential amplifier AD8275 whose output is connected to a 16-bit, 250 kSPS MSOP/QFN packaged PulSAR. Input terminal of ADC AD7685. The AD8226 has a gain set to 1 (high voltage/current input) and its output is referenced to ground. Single-ended or differential inputs can be used. The output of the AD8226 is a bipolar signal used to drive the AD8275 input. The AD8275 is used to attenuate and level shift this bipolar input, providing a gain of 0.2. Therefore, when a differential signal of 20 V pp is input at its input terminal, a single-ended signal of 4 V pp will be generated at the output terminal. The ADR439 4.5 V precision voltage reference is used to provide the internal common-mode bias voltage (VREF/2 = 2.25V) for the AD8275 and the external reference voltage for the AD7685 ADC. Under these conditions, the AD8275's output swings from +0.25 V to +4.25 V, which is within the 0 V to +4.5 V operating range of the AD7685.

The ADP1720 is used to provide the 5 V power supply for the AD8275 and AD7685. The ADP1720 was chosen because of its high input voltage range (up to 28 V). In this circuit, the ADP1720 only needs to supply about 4 mA to the AD8275 and AD7685, so the regulator dissipates about 90 mW in the worst case at a 28 V input, which allows the entire system to operate with an external ±15 V Mains power supply.


System-Level Common-Mode Rejection Performance


Initial testing is used to verify the AD8226 common-mode rejection performance at the system level to the ADC. The input test signal tones used are 10 Hz, 100 Hz, 500 Hz, 1 kHz, 2 kHz, 3 kHz, 4 kHz, 5 kHz, and the input signal is 18 V pp. The test results are shown in Table 1. In test 1, the AIN+ and AIN− signals are shorted and connected to the AC test tone, and the results are measured in FFT. Since the inputs are connected together, the AD8226 should reject the AC signal. In test 2, the signal is applied to AIN+ and AIN− is connected to ground. Under these conditions, the FFT measures the tone level. The common mode rejection value is then obtained by calculating the difference between the FFT results in Test 1 and Test 2. Table 1 lists the CMR values ​​obtained at different frequencies. It is important to note that the AD8226 has a CMR rating of 80 dB at 5 kHz, so no loss of CMR performance is achieved at the system level.


System-level AC performance


In addition, the AC accuracy of the system must be tested at the system level. At this time, the operating sampling rate of the AD7685 is 250 kSPS. Figure 2 shows the FFT test results at 10 kHz, 5 V pp input. The results shown in the graph are as follows:

  • Signal-to-noise ratio (SNR) = 87.13 dBFS
  • SINAD = 85.95 dBFS
  • Spurious-free dynamic range (SFDR) = 81.82 dBc
  • Total harmonic distortion (THD) = −78.02 dBc


Table 1: CMR performance of the circuit at 18 V pp input
Frequency (kHz)
FFT Signal Level (dBFS), 18 Vpp Input
CMR(db)
Test 1: AIN+ = AIN-
Test 2: Input=AIN+, AIN- =GNO
0.1 -104.64
-2.86
101.78
0.5
-100.00
-3.28
96.72
1
-94.67
-2.85
91.82
2
-88.58
-2.88
85.70
3
-84.93
-2.93
82.00
4
-82.07
-3.01
79.06
5
-79.43
-3.10
76.33

 

Figure 2. FFT results for 10 kHz input signal, 14 dB below full scale, 250 kSPS

 

The performance of this or any high-speed circuit is highly dependent on proper PCB layout, including but not limited to power supply bypassing, controlled impedance lines (if required), component placement, signal routing, and power and ground planes. (For more information on PCB layout, see the MT-031 Tutorial , MT-101 Tutorial , and the Practical Guide to High-Speed ​​Printed Circuit Board Layout articles.)

For a complete design support package for this circuit note, see http://www.analog.com/CN0213-DesignSupport

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