REP021: Front-end devices for 2.5GHz Globalstar and IS-95

This reference design (RD) is for a dual-band CDMA front-end IC that uses a PCS-band signal path for 2.5GHz LEO satellite channel and a cellular-band signal path for GlobalStar IS-95 CDMA applications. The MAX2323 LNA plus mixer for dual-band CDMA handsets is featured.

Schematic PCB

REP017: Dual-band three-mode IC suitable for both CDMA and AMPS with an intermediate frequency of 183MHz

Reference design (RD) is a dual-band, triple-mode CDMA front-end to a receiver whose frequency plan requires digital and AMPS analog IFs to be at 183.6MHz. RD uses the MAX2338, a low-noise amplifier (LNA) with mixer, that is useful for TDMA, GSM, EDGE, and WCDMA applications.

Schematic PCB

OM13536: SA639DH Demonstration Board

ALCATRAZ (MAXREFDES34#): SHA-256 security authentication design

The Alcatraz (MAXREFDES34#) subsystem provides a reference design for securing Xilinx FPGAs to protect IP and prevent attached peripheral counterfeiting. The system implements a SHA-256 challenge-response between the FPGA and a DS28E15 secure authenticator. Boards for purchase, hardware, and firmware design files provide complete system information for rapid prototyping and development.

Schematic PCB

REP003: Cellular Front-End ICs in Automotive Applications

This reference design (RD) is for a dual-band CDMA front-end IC for use in automotive applications. The application circuit uses the MAX2323 low-noise amplifier (LNA) with mixer at temperatures up to 110°C. The device is also useful for TDMA, GSM, EDGE, and WCDMA applications. Schematics, bill of materials (BOM), and performance measurements are shown.

Schematic PCB

REP018: Dual-band dual-mode FE IC operating at universal 183.6MHz IF

Reference design (RD) is a dual-band, triple-mode CDMA front-end IC in a receiver with all 183MHz IFs for processing cellular CDMA. The RD uses the MAX2323, a low-noise amplifier (LNA) with mixer, that is useful for TDMA, GSM, EDGE, and WCDMA applications.

Schematic PCB

REP016: Japanese 110MHz IF dual-band cellular CDMA RF front-end

This reference design (RD) is for a dual-band, dual-mode CDMA front-end for Japanese cellular CDMA at 110MHz IF. The RD uses a low-noise amplifier (LNA) with mixer, the MAX2325, that is also useful for TDMA, GSM, and EDGE applications. Schematics and bill of materials are shown.

Schematic PCB

CN0287

Isolated 4-Channel Thermocouple/RTD Temperature Measurement System with 0.5°C Accuracy

Schematic PCB

Design 8-channel asynchronous ADC acquisition into synchronous acquisition through phase compensation

A phase compensation algorithm is used to compensate for the additional phase delay introduced by the multiplexed ADC, thereby producing an effect equivalent to a synchronously sampled ADC.

Schematic PCB

CN0234

Single-supply, micropower toxic gas detector using electrochemical sensors

Schematic PCB

CN0255

16-bit, 100 kSPS single-supply low-power data acquisition system

Schematic PCB

pmod-gnss：GNSS PMOD、GPS + Glonass

This design is a PMOD with the ublox NEO GNSS receiver footprint. Able to receive GPS and GLONASS simultaneously.

Schematic PCB

CN0326

Isolated, low-power pH monitor with temperature compensation

Schematic PCB

CN0247

12-bit, 1 MSPS SAR ADC and driver, total power consumption is less than 5 mW

Schematic PCB

OM13530: SA6x4AHR Evaluation Demonstration Board

TI high-speed oscilloscope reference design (sampling rate 12.8Gsps, bandwidth 6GHz, 12bit resolution)

The complete PCB related files are open source, and there is also a design document for reference and study.

Schematic PCB

CN0277

18-bit, 5 MSPS data acquisition system optimized for AC performance

Schematic PCB

OM13312: SA636DK Evaluation Demonstration Board

The SA636DK evaluation demonstration board is used to evaluate the RF development platform for 110.592 MHz RF and 9.8 MHz IF.

CN0254

16-bit, 250 kSPS, 8-channel single-supply isolated data acquisition system

Schematic PCB

12-Bit, 2GSPS Data Acquisition Reference Design

By interleaving Renesas' low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs. This reference design demonstrates the performance attainable by combining Renesas' ADC technology and SP Devices' interleaving algorithms. In this design, four ISLA112P50 12-bit, 500MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC.